PDF PI7C9X110 Data sheet ( Hoja de datos )

Número de pieza	PI7C9X110
Descripción	PCI Express-to-PCI Reversible Bridge
Fabricantes	Pericom Semiconductor Corporation
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No Preview Available ! www.DataSheet4U.com PI7C9X110 PCI Express-to-PCI Reversible Bridge Revision 2.4 3545 North 1ST Street, San Jose, CA 95134 Phone: 1-877-PERICOM (1-877-737-4266) FAX: 1-408-435-1100 Internet: http://www.pericom.com 1 page www.DataSheet4U.com PI7C9X110 PCIe-to-PCI Reversible Bridge 7.4.15 7.4.16 7.4.17 7.4.18 7.4.19 7.4.20 7.4.21 7.4.22 7.4.23 7.4.24 7.4.25 7.4.26 7.4.27 7.4.28 7.4.29 7.4.30 7.4.31 7.4.32 7.4.33 7.4.34 7.4.35 7.4.36 7.4.37 7.4.38 7.4.39 7.4.40 7.4.41 7.4.42 7.4.43 7.4.44 7.4.45 7.4.46 7.4.47 7.4.48 7.4.49 7.4.50 7.4.51 7.4.52 7.4.53 7.4.54 7.4.55 7.4.56 7.4.57 7.4.58 7.4.59 7.4.60 7.4.61 7.4.62 7.4.63 7.4.64 7.4.65 7.4.66 I/O BASE REGISTER – OFFSET 1Ch.................................................................................................. 37 I/O LIMIT REGISTER – OFFSET 1Ch................................................................................................. 37 SECONDARY STATUS REGISTER – OFFSET 1Ch ............................................................................ 37 MEMORY BASE REGISTER – OFFSET 20h ....................................................................................... 38 MEMORY LIMIT REGISTER – OFFSET 20h ...................................................................................... 38 PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h......................................................... 38 PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h........................................................ 38 PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h................................................. 40 PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch............................................... 40 I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h......................................................................... 40 I/O LIMIT UPPER 16-BIT REGISTER – OFFSET 30h........................................................................ 40 CAPABILITY POINTER – OFFSET 34h .............................................................................................. 40 EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h ....................................................... 40 INTERRUPT LINE REGISTER – OFFSET 3Ch................................................................................... 40 INTERRUPT PIN REGISTER – OFFSET 3Ch ..................................................................................... 41 BRIDGE CONTROL REGISTER – OFFSET 3Ch ................................................................................ 41 PCI DATA BUFFERING CONTROL REGISTER – OFFSET 40h ....................................................... 42 CHIP CONTROL 0 REGISTER – OFFSET 40h................................................................................... 43 RESERVED REGISTER – OFFSET 44h............................................................................................... 46 ARBITER ENABLE REGISTER – OFFSET 48h................................................................................... 46 ARBITER MODE REGISTER – OFFSET 48h...................................................................................... 46 ARBITER PRIORITY REGISTER – OFFSET 48h ................................................................................ 47 RESERVED REGISTERS – OFFSET 4Ch – 64h .................................................................................. 48 EXPRESS TRANSMITTER/RECEIVER REGISTER – OFFSET 68h.................................................... 48 UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER – OFFSET 68h ....................... 49 RESERVED REGISTER – OFFSET 6Ch .............................................................................................. 49 EEPROM AUTOLOAD CONTROL/STATUS REGISTER – OFFSET 70h........................................... 49 RESERVED REGISTER – OFFSET 74h............................................................................................... 51 GPIO DATA AND CONTROL REGISTER – OFFSET 78h.................................................................. 51 RESERVED REGISTER – OFFSET 7Ch .............................................................................................. 51 PCI-X CAPABILITY ID REGISTER – OFFSET 80h ............................................................................ 51 NEXT CAPABILITY POINTER REGISTER – OFFSET 80h ................................................................ 51 PCI-X SECONDARY STATUS REGISTER – OFFSET 80h.................................................................. 51 PCI-X BRIDGE STATUS REGISTER – OFFSET 84h.......................................................................... 52 UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h ........................................................ 53 DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch ................................................. 53 POWER MANAGEMENT ID REGISTER – OFFSET 90h.................................................................... 54 NEXT CAPABILITY POINTER REGISTER – OFFSET 90h ................................................................ 54 POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h .................................................. 54 POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h .............................. 55 PCI-TO-PCI SUPPORT EXTENSION REGISTER – OFFSET 94h ..................................................... 55 RESERVED REGISTERS – OFFSET 98h – 9Ch .................................................................................. 55 CAPABILITY ID REGISTER – OFFSET A0h....................................................................................... 55 NEXT POINTER REGISTER – OFFSET A0h....................................................................................... 55 SLOT NUMBER REGISTER – OFFSET A0h ....................................................................................... 56 CHASSIS NUMBER REGISTER – OFFSET A0h ................................................................................. 56 SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h................................. 56 CAPABILITY ID REGISTER – OFFSET A8h....................................................................................... 57 NEXT POINTER REGISTER – OFFSET A8h....................................................................................... 57 RESERVED REGISTER – OFFSET A8h .............................................................................................. 57 SUBSYSTEM VENDOR ID REGISTER – OFFSET ACh...................................................................... 58 SUBSYSTEM ID REGISTER – OFFSET ACh ...................................................................................... 58 Pericom Semiconductor Page 5 of 145 November 2007, Revision 2.4 5 Page www.DataSheet4U.com PI7C9X110 PCIe-to-PCI Reversible Bridge 16.1 ABSOLUTE MAXIMUM RATINGS .............................................................................................................. 141 16.2 DC SPECIFICATIONS..................................................................................................................................... 141 16.3 AC SPECIFICATIONS..................................................................................................................................... 142 17 PACKAGE INFORMATION................................................................................................ 143 18 ORDERING INFORMATION.............................................................................................. 144 Pericom Semiconductor Page 11 of 145 November 2007, Revision 2.4 11 Page

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Número de pieza	Descripción	Fabricantes
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