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Número de pieza | BUK9520-55A | |
Descripción | (BUK9520-55A / BUK9620-55A) TrenchMOS logic level FET | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
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BUK9520-55A; BUK9620-55A
TrenchMOS™ logic level FET
Rev. 01 — 29 January 2001
Product specification
1. Description
N-channel enhancement mode field-effect power transistor in a plastic package using
TrenchMOS™ technology, featuring very low on-state resistance.
Product availability:
BUK9520-55A in SOT78 (TO-220AB)
BUK9620-55A in SOT404 (D 2-PAK).
2. Features
s TrenchMOS™ technology
s Q101 compliant
s 175 °C rated
s Logic level compatible.
3. Applications
s Automotive and general purpose power switching:
c
c x 12 V and 24 V loads
x Motors, lamps and solenoids.
4. Pinning information
Table 1: Pinning - SOT78 and SOT404, simplified outline and symbol
Pin Description
Simplified outline
1 gate (g)
2 drain (d)
mb
mb
3 source (s)
mb mounting base;
connected to drain (d)
MBK106
123
SOT78 (TO-220AB)
2
1 3 MBK116
SOT404 (D2-PAK)
Symbol
d
g
MBB076
s
1 page Philips Semiconductors
www.DataSheet4U.com
BUK9520-55A; BUK9620-55A
TrenchMOS™ logic level FET
8. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified
Symbol Parameter
Conditions
Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source breakdown
ID = 0.25 mA; VGS = 0 V
voltage
Tj = 25 °C
55 − − V
Tj = −55 °C
50 − − V
VGS(th)
gate-source threshold voltage ID = 1 mA; VDS = VGS;
Figure 9
IDSS
IGSS
RDSon
drain-source leakage current
gate-source leakage current
drain-source on-state
resistance
Tj = 25 °C
Tj = 175 °C
Tj = −55 °C
VDS = 55 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
VGS = ±10 V; VDS = 0 V
VGS = 5 V; ID = 25 A;
Figure 7 and 8
1 1.5 2 V
0.5 − − V
− − 2.3 V
−
0.05 10
µA
− − 500 µA
− 2 100 nA
Dynamic characteristics
Tj = 25 °C
Tj = 175 °C
VGS = 4.5 V; ID = 25 A
VGS = 10 V; ID = 25 A
− 17 20 mΩ
− − 40 mΩ
− − 21 mΩ
− 15 18 mΩ
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
Ld
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
internal drain inductance
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Figure 12
VDD = 30 V; RL = 1.2 Ω;
VGS = 5 V; RG = 10 Ω
from drain lead 6 mm from
package to centre of die
−
−
−
−
−
−
−
−
1660
290
194
19
124
92
93
4.5
2210
346
266
−
−
−
−
−
pF
pF
pF
ns
ns
ns
ns
nH
from contact screw on
mounting base to centre of
die SOT78
−
3.5 −
nH
from upper edge of drain
mounting base to centre of
die SOT404
−
2.5 −
nH
Ls
internal source inductance from source lead to source
−
bond pad
7.5 −
nH
9397 750 07794
Product specification
Rev. 01 — 29 January 2001
© Philips Electronics N.V. 2001. All rights reserved.
5 of 15
5 Page Philips Semiconductors
www.DataSheet4U.com
10. Soldering
BUK9520-55A; BUK9620-55A
TrenchMOS™ logic level FET
handbook, full pagewidth
1.50
2.25 2.15
10.85
10.60
10.50
7.50
7.40
1.70
8.15 8.35
1.50
4.60
8.275
4.85
7.95
0.30
3.00
solder lands
solder resist
occupied area
solder paste
Dimensions in mm.
Fig 18. Reflow soldering footprint for SOT404.
5.40
8.075
0.20
5.08
1.20
1.30
1.55
MSD057
9397 750 07794
Product specification
Rev. 01 — 29 January 2001
© Philips Electronics N.V. 2001. All rights reserved.
11 of 15
11 Page |
Páginas | Total 15 Páginas | |
PDF Descargar | [ Datasheet BUK9520-55A.PDF ] |
Número de pieza | Descripción | Fabricantes |
BUK9520-55 | TrenchMOS transistor Logic level FET | NXP Semiconductors |
BUK9520-55 | TrenchMOS transistor Logic level FET | NXP Semiconductors |
BUK9520-55A | (BUK9520-55A / BUK9620-55A) TrenchMOS logic level FET | NXP Semiconductors |
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