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PDF APL0915 Data sheet ( Hoja de datos )

Número de pieza APL0915
Descripción PLL Module
Fabricantes Advanced Semiconductor Business 
Logotipo Advanced Semiconductor Business Logotipo



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No Preview Available ! APL0915 Hoja de datos, Descripción, Manual

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Features
· +0dBm Output Level at 915 MHz
· Channel Step Size : 200 kHz
· 2nd Harmonic : < - 35dBc
· Spurious Level : < - 70dBc
· Lock Time : < 1ms
· 30mA Current Consumption
· Strip-line Resonator
Description
The plerowTM PLL synthesizer module was
designed for use in wireless and wireline
systems in a wide range of frequency from
50 MHz to 6 GHz. ASB’s PLL provides ex-
ceptionally low spurious and phase noise
performance with fast locking time and low
current consumption. All products are avail-
able in a surface-mount type package.
Specifications
Parameter
Unit Min.
Typical
Max.
Frequency Range
MHz
900
915
930
Output Power
dBm
-2
0
2
Supply Voltage
V 4.7 5 5.3
Current Consumption
mA
30
Channel Step Size
2nd Harmonics
kHz
dBc
200
-45 -35
Spurious Level
dBc
-70
Lock Time
ms
1
Reference Frequency
MHz
10
Reference Input Level
dBm
-5
2
7
Phase Noise (C / N)
@ 1 kHz
@ 10 kHz
@ 100 kHz
dBc/Hz
-107
-120
-104
-118
Output Impedance
Operating Temp. Range
Package Type & Size
50
°C -40
25
85
mm SMT, 19.0W×19.0L×5.8H
1) Measurement conditions are as follows: T = 25°C, VCC = 5.0 V, Freq. = 915 MHz, 50 ohm system.
Plerow APL0915
PLL Module
More Information
Website: www.asb.co.kr
Tel: (82) 42-528-7220
Fax: (82) 42-528-7222
ASB Inc., 4th Fl. Venture Town
Bldg., 367-17 Goijeong-Dong,
Seo-Gu, Daejon 302-716, Korea
Outline Drawing
Top View
A
C
B
Side View
1/1
Bottom View
I
HG
D
E
F
Pin Configuration
1 CLOCK
2 DATA
3 ENABLE
4 OSC IN
9 VCC (VCO)
13 RF OUT
15 VCP (PLL)
16 LOCK DETECT
Others
Ground
Dimension (mm)
A 19.0
B 19.0
C 5.8
D 1.5
E 0.5
F 1.75
G 1.35
H 15.0
I 0.9
Tolerance: ± 0.2
www.asb.co.kr
December 2004

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