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PDF LTC3851-1 Data sheet ( Hoja de datos )
| Número de pieza | LTC3851-1 | |
| Descripción | Synchronous Step-Down Switching Regulator Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURESwww.datasheet4u.com
n Wide VIN Range: 4V to 38V Operation
n RSENSE or DCR Current Sensing
n ±1% Output Voltage Accuracy
n Power Good Output Voltage Monitor
n Phase-Lockable Fixed Frequency: 250kHz to 750kHz
n Dual N-Channel MOSFET Synchronous Drive
n Very Low Dropout Operation: 99% Duty Cycle
n Adjustable Output Voltage Soft-Start or Tracking
n Output Current Foldback Limiting
n Output Overvoltage Protection
n OPTI-LOOP® Compensation Minimizes COUT
n Selectable Continuous, Pulse-Skipping or
Burst Mode® Operation at Light Loads
n Low Shutdown IQ: 20μA
n VOUT Range: 0.8V to 5.5V
n Thermally Enhanced 16-Lead MSOP
or 3mm × 3mm QFN Package
APPLICATIONS
n Automotive Systems
n Telecom Systems
n Industrial Equipment
n Distributed DC Power Systems
LTC3851-1
Synchronous
Step-Down Switching
Regulator Controller
DESCRIPTION
The LTC®3851-1 is a high performance synchronous
step-down switching regulator controller that drives
an all N-channel synchronous power MOSFET stage. A
constant frequency current mode architecture allows a
phase-lockable frequency of up to 750kHz.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The LTC3851-1 features a precision 0.8V
reference and a power good indicator. A wide 4V to 38V (40V
absolute maximum) input supply range encompasses most
battery configurations and intermediate bus voltages.
The TK/SS pin ramps the output voltage during start-up
and shutdown with coincident or ratiometric tracking.
Current foldback limits MOSFET heat dissipation during
short-circuit conditions. The MODE/PLLIN pin selects
among Burst Mode operation, pulse skipping mode or
continuous inductor current mode at light loads and allows
the IC to be synchronized to an external clock.
The LTC3851-1 is identical to the LTC3851 except that the
ILIM pin is replaced by PGOOD.
L, LT, LTC, LTM, Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5408150, 5481178, 5705919, 5929620, 6304066,
6498466, 6580258, 6611131.
TYPICAL APPLICATION
High Efficiency Synchronous Step-Down Converter
INTVCC
82.5k
100k
PGO0D
VIN
0.1μF
0.1μF
FREQ/PLLFLTR TG
RUN SW
LTC3851-1
TK/SS BOOST
0.1μF
0.68μH
3.01k
22μF
VIN
4.5V TO 38V
VOUT
3.3V
15A
330μF
s2
2200pF
15k
INTVCC
ITH
330pF
BG
GND
SENSE+
PLLIN/MODE
SENSE–
VFB
4.7μF
0.047μF 30.1k
154k
48.7k
38511 TA01a
Efficiency and Power Loss
vs Load Current
100
VIN = 12V
95 VOUT = 3.3V
90
EFFICIENCY
10000
85 1000
80
POWER LOSS
75
70
65 100
60
55
50
10
10
100 1000 10000 100000
LOAD CURRENT (mA)
38511TA01b
38511f
1
1 page  
TYPICAL PERFORMANCE CHARACTERISTICS
LTC3851-1
Efficiency and Power Loss vs
Input Voltage
www.d10a0tasheet4u.com
EFFICIENCY,
95 IOUT = 5A
90
POWER LOSS,
IOUT = 5A
10000
Load Step
(Burst Mode Operation)
ILOAD
5A/DIV
0.2A TO 7.5A
IL
5A/DIV
85
80
75
70
4
EFFICIENCY,
IOUT = 0.5A
1000
POWER LOSS,
IOUT = 0.5A
8 12 16
VIN = 12V
VOUT = 3.3V
FIGURE 11 CIRCUIT
100
20 24 28 32
INPUT VOLTAGE (V)
38511 G04
VOUT
100mV/DIV
AC COUPLED
VOUT = 1.5V
100μs/DIV
VIN = 12V
FIGURE 11 CIRCUIT
Load Step
(Forced Continuous Mode)
ILOAD
5A/DIV
0.2A TO 7.5A
IL
5A/DIV
VOUT
100mV/DIV
AC COUPLED
38511 G05
VOUT = 1.5V
100μs/DIV
VIN = 12V
FIGURE 11 CIRCUIT
38511 G06
Load Step
(Pulse skip Mode)
Inductor Current at Light Load
Start-Up with Prebiased Output
at 2V
ILOAD
5A/DIV
0.2A TO 7.5A
IL
5A/DIV
VOUT
100mV/DIV
AC COUPLED
VOUT = 1.5V
100μs/DIV
VIN = 12V
FIGURE 11 CIRCUIT
FORCED
CONTINOUS
MODE
5A/DIV
Burst Mode
OPERATION
5A/DIV
3851 G07
PULSE SKIP
MODE
5A/DIV
VOUT = 1.5V
1μs/DIV
VIN = 12V
ILOAD = 1mA
FIGURE 11 CIRCUIT
VOUT
2V/DIV
VFB
0.5V/DIV
38511 G08
TK/SS
0.5V/DIV
20ms/DIV
38511 G09
Coincident Tracking with Master
Supply
VMASTER
0.5V/DIV
VOUT
2A LOAD
0.5V/DIV
10ms/DIV
38511 G10
Ratiometric Tracking with Master
Supply
VMASTER
0.5V/DIV
VOUT
2A LOAD
0.5V/DIV
10ms/DIV
38511 G11
Input DC Supply Current vs Input
Voltage
3.0
2.5
2.0
1.5
1.0
0.5
0
4 8 12 16 20 24 28 32 36 40
INPUT VOLTAGE (V)
38511 G12
38511f
5
5 Page 
LTC3851-1
OPERATION
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output
wwwb.deagtaisnhseteot4rui.sceom. When the output voltage drops enough, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top external MOSFET on the
next cycle of the internal oscillator. When a controller is
enabled for Burst Mode operation, the inductor current is
not allowed to reverse. The reverse current comparator,
IREV, turns off the bottom external MOSFET just before the
inductor current reaches zero, preventing it from revers-
ing and going negative. Thus, the controller operates in
discontinuous operation. In forced continuous operation,
the inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor cur-
rent is determined by the voltage on the ITH pin, just as in
normal operation. In this mode the efficiency at light loads
is lower than in Burst Mode operation. However, continu-
ous mode has the advantages of lower output ripple and
less interference to audio circuitry.
When the MODE/PLLIN pin is connected to GND, the
LTC3851-1 operates in PWM pulse skipping mode at
light loads. At very light loads the current comparator,
ICMP, may remain tripped for several cycles and force the
external top MOSFET to stay off for the same number of
cycles (i.e., skipping pulses). The inductor current is not
allowed to reverse (discontinuous operation). This mode,
like forced continuous operation, exhibits low output ripple
as well as low audio noise and reduced RF interference
as compared to Burst Mode operation. It provides higher
low current efficiency than forced continuous mode, but
not nearly as high as Burst Mode operation.
Frequency Selection and Phase-Locked Loop
(FREQ/PLLFLTR and MODE/PLLIN Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching losses,
but requires larger inductance and/or capacitance to main-
tain low output ripple voltage. The switching frequency of
the LTC3851-1 can be selected using the FREQ/PLLFLTR
pin. If the MODE/PLLIN pin is not being driven by an ex-
ternal clock source, the FREQ/PLLFLTR pin can be used
to program the controller’s operating frequency from
250kHz to 750kHz.
A phase-locked loop (PLL) is available on the LTC3851-1
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The
controller operates in forced continuous mode of operation
when it is synchronized. A series RC should be connected
between the FREQ/PLLFLTR pin and GND to serve as the
PLL’s loop filter.
It is suggested that the external clock be applied before
enabling the controller unless a second resistor is con-
nected in parallel with the series RC loop filter network.
The second resistor prevents low switching frequency
operation if the controller is enabled before the clock.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious con-
ditions that may overvoltage the output. In such cases,
the top MOSFET is turned off and the bottom MOSFET is
turned on until the overvoltage condition is cleared.
Power Good (PGOOD) Pin
The PGOOD pin is connected to an open drain of an internal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when the VFB pin voltage is not within
±10% of the 0.8V reference voltage. The PGOOD pin is
also pulled low when the RUN pin is low (shut down) or
when the LTC3851-1 is in the soft-start or tracking phase.
When the VFB pin voltage is within the ±10% requirement,
the MOSFET is turned off and the pin is allowed to be
pulled up by an external resistor to a source of up to 6V.
The PGOOD pin will flag power good immediately when
the VFB pin is within the ±10% window. However, there is
an internal 17μs power bad mask when VFB goes out of
the ±10% window.
38511f
11
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| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC3851-1.PDF ] | |
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