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PDF LTC2248 Data sheet ( Hoja de datos )
| Número de pieza | LTC2248 | |
| Descripción | (LTC2246 - LTC2248) 65/40/25Msps Low Power 3V ADCs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC2248 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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FEATURES
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■ Sample Rate: 65Msps/40Msps/25Msps
■ Single 3V Supply (2.7V to 3.4V)
■ Low Power: 205mW/120mW/75mW
■ 74.3dB SNR
■ 90dB SFDR
■ No Missing Codes
■ Flexible Input: 1VP-P to 2VP-P Range
■ 575MHz Full Power Bandwidth S/H
■ Clock Duty Cycle Stabilizer
■ Shutdown and Nap Modes
■ Pin Compatible Family
125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit)
105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit)
80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit)
65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit)
40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit)
25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit)
10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit)
■ 32-Pin (5mm × 5mm) QFN Package
U
APPLICATIO S
■ Wireless and Wired Broadband Communication
■ Imaging Systems
■ Ultrasound
■ Spectral Analysis
■ Portable Instrumentation
LTC2248/LTC2247/LTC2246
14-Bit, 65/40/25Msps
Low Power 3V ADCs
DESCRIPTIO
The LTC®2248/LTC2247/LTC2246 are 14-bit 65Msps/
40Msps/25Msps, low power 3V A/D converters designed
for digitizing high frequency, wide dynamic range signals.
The LTC2248/LTC2247/LTC2246 are perfect for demand-
ing imaging and communications applications with AC
performance that includes 74.3dB SNR and 90dB SFDR
for signals at the Nyquist frequency.
DC specs include ±1LSB INL (typ), ±0.5LSB DNL (typ) and
no missing codes over temperature. The transition noise
is a low 1LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
REFH
REFL
FLEXIBLE
REFERENCE
ANALOG
INPUT
+
INPUT
S/H
–
14-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
CLOCK/DUTY
CYCLE
CONTROL
CLK
OUTPUT
DRIVERS
OVDD
D13
•
•
•
D0
OGND
2249 TA01a
LTC2248: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
75
74
73
72
71
70
0 50 100 150 200
INPUT FREQUENCY (MHZ)
2249 TAO1b
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1 page  
LTC2248/LTC2247/LTC2246
WU
TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
wwwf.sdatasheeSt4aum.pcloinmg Frequency (Note 9)
tL
CLK Low Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
●
●
●
tH
CLK High Time
Duty Cycle Stabilizer Off ●
Duty Cycle Stabilizer On ●
(Note 7)
tAP Sample-and-Hold
Aperture Delay
tD
CLK to DATA delay CL = 5pF (Note 7)
●
Data Access Time CL = 5pF (Note 7)
After OE↓
●
BUS Relinquish Time (Note 7)
●
Pipeline
Latency
LTC2248
MIN TYP MAX
1 65
7.3 7.7 500
5 7.7 500
7.3 7.7 500
5 7.7 500
0
1.4 2.7 5.4
4.3 10
3.3 8.5
5
LTC2247
MIN TYP MAX
1 40
11.8 12.5 500
5 12.5 500
11.8 12.5 500
5 12.5 500
0
1.4 2.7 5.4
4.3 10
3.3 8.5
5
LTC2246
MIN TYP MAX
1 25
18.9 20 500
5 20 500
18.9 20 500
5 20 500
0
1.4 2.7 5.4
4.3 10
3.3 8.5
5
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 65MHz (LTC2248), 40MHz (LTC2247), or
25MHz (LTC2246), input range = 2VP-P with differential drive, unless
otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and
11 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 65MHz (LTC2248), 40MHz (LTC2247), or
25MHz (LTC2246), input range = 1VP-P with differential drive.
Note 9: Recommended operating conditions.
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2248: Typical INL,
2V Range, 65Msps
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
4096
8192
CODE
12288 16384
2248 G01
LTC2248: Typical DNL,
2V Range, 65Msps
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
0
4096
8192
CODE
12288 16384
2248 G02
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LTC2248/LTC2247/LTC2246
PI FU CTIO S
AIN+ (Pin 1): Positive Differential Analog Input.
AIN- (Pin 2): Negative Differential Analog Input.
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REFH (Pins 3, 4): ADC High Reference. Short together and
bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 5, 6 with
an additional 2.2µF ceramic chip capacitor and to ground
with a 1µF ceramic chip capacitor.
REFL (Pins 5, 6): ADC Low Reference. Short together and
bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 3, 4 with
an additional 2.2µF ceramic chip capacitor and to ground
with a 1µF ceramic chip capacitor.
VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF
ceramic chip capacitors.
GND (Pin 8): ADC Power Ground.
CLK (Pin 9): Clock Input. The input sample starts on the
positive edge.
SHDN (Pin 10): Shutdown Mode Selection Pin. Connect-
ing SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to VDD results in normal operation with the
outputs at high impedance. Connecting SHDN to VDD and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to VDD and OE to VDD
results in sleep mode with the outputs at high impedance.
OE (Pin 11): Output Enable Pin. Refer to SHDN pin
function.
D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24,
25, 26, 27): Digital Outputs. D13 is the MSB.
OGND (Pin 20): Output Driver Ground.
OVDD (Pin 21): Positive Supply for the Output Drivers.
Bypass to ground with 0.1µF ceramic chip capacitor.
OF (Pin 28): Over/Under Flow Output. High when an over
or under flow has occurred.
MODE (Pin 29): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
offset binary output format and turns the clock duty cycle
stabilizer off. 1/3 VDD selects offset binary output format
and turns the clock duty cycle stabilizer on. 2/3 VDD selects
2’s complement output format and turns the clock duty
cycle stabilizer on. VDD selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
SENSE (Pin 30): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. VDD selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±VSENSE. ±1V is the largest valid input range.
VCM (Pin 31): 1.5V Output and Input Common Mode Bias.
Bypass to ground with 2.2µF ceramic chip capacitor.
GND (Exposed Pad) (Pin 33): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
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11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC2248.PDF ] | |
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