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PDF LTC2240-12 Data sheet ( Hoja de datos )
| Número de pieza | LTC2240-12 | |
| Descripción | 170Msps ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC2240-12
12-Bit, 170Msps ADC
FEATURES
www.datasheet4u.com
n Sample Rate: 170Msps
n 65.6dB SNR
n 80dB SFDR
n 1.2GHz Full Power Bandwidth S/H
n Single 2.5V Supply
n Low Power Dissipation: 445mW
n LVDS, CMOS, or Demultiplexed CMOS Outputs
n Selectable Input Ranges: ±0.5V or ±1V
n No Missing Codes
n Optional Clock Duty Cycle Stabilizer
n Shutdown and Nap Modes
n Data Ready Output Clock
n Pin Compatible Family
250Msps: LTC2242-12 (12-Bit), LTC2242-10 (10-Bit)
210Msps: LTC2241-12 (12-Bit), LTC2241-10 (10-Bit)
170Msps: LTC2240-12 (12-Bit), LTC2240-10 (10-Bit)
185Msps: LTC2220-1 (12-Bit)*
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)*
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)*
n 64-Pin 9mm × 9mm QFN Package
APPLICATIONS
n Wireless and Wired Broadband Communication
n Cable Head-End Systems
n Power Amplifier Linearization
n Communications Test Equipment
DESCRIPTION
The LTC®2240-12 is a 170Msps, sampling 12-bit A/D con-
verter designed for digitizing high frequency, wide dynamic
range signals. The LTC2240-12 is perfect for demanding
communications applications with AC performance that
includes 65.6dB SNR and 80dB SFDR. Ultralow jitter of
95fsRMS allows IF undersampling with excellent noise
performance.
DC specs include ±0.6LSB INL (typ), ±0.4LSB DNL (typ)
and no missing codes over temperature.
The digital outputs can be either differential LVDS, or
single-ended CMOS. There are three format options for
the CMOS outputs: a single bus running at the full data
rate or two demultiplexed buses running at half data rate
with either interleaved or simultaneous update. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 2.625V.
The ENC+ and ENC– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance over a wide range of clock duty cycles.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
*LTC2220-1, LTC2220, LTC2221, LTC2230, LTC2231 are 3.3V parts.
TYPICAL APPLICATION
REFH
REFL
FLEXIBLE
REFERENCE
2.5V
VDD
ANALOG
INPUT
+
INPUT
S/H
–
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
CLOCK/DUTY
CYCLE
CONTROL
ENCODE
INPUT
OUTPUT
DRIVERS
0.5V
TO 2.625V
OVDD
D11
• CMOS
• OR
• LVDS
D0
OGND
224012 TA01
SNR vs Input Frequency
85
80
75
70
65
1V RANGE
60
2V RANGE
55
50
45
40
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
224012 G11
224012fb
1
1 page  
LTC2240-12
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
LOGIC OUTPUTS (LVDS MODE)
www.datasheet4u.com
VOD Differential Output Voltage
100Ω Differential Load
l 247 350 454
mV
VOS
Output Common Mode Voltage
100Ω Differential Load
l 1.125 1.250 1.375
V
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VDD Analog Supply Voltage
PSLEEP
Sleep Mode Power
PNAP Nap Mode Power
LVDS OUTPUT MOD
(Note 8)
SHDN = High, OE = High, No CLK
SHDN = High, OE = Low, No CLK
l 2.375 2.5 2.625
1
28
V
mW
mW
OVDD
Output Supply Voltag
IVDD Analog Supply Current
IOVDD
Output Supply Current
PDISS
Power Dissipation
CMOS OUTPUT MODE
(Note 8)
l 2.375 2.5 2.625
l 170 185
l 58 70
l 570 638
V
mA
mA
mW
OVDD
IVDD
PDISS
Output Supply Voltage
Analog Supply Current
Power Dissipation
(Note 8)
(Note 7)
l 0.5
l
2.5 2.625
170 185
445
V
mA
mW
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
fS Sampling Frequency
(Note 8)
tL
ENC Low Time (Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l1
170
l 2.79 2.94 500
l 1.5 2.94 500
MHz
ns
ns
tH
ENC High Time (Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l 2.79 2.94 500
l 1.5 2.94 500
ns
ns
tAP Sample-and-Hold Aperture Delay
tOE Output Enable Delay
(Note 7)
0.4 ns
l
5 10
ns
LVDS OUTPUT MODE
tD ENC to DATA Delay
(Note 7)
tC ENC to CLKOUT Delay
(Note 7)
DATA to CLKOUT Skew
(tC – tD) (Note 7)
Rise Time
l1
l1
l –0.6
1.7
1.7
0
0.5
2.8
2.8
0.6
ns
ns
ns
ns
Fall Time
0.5 ns
Pipeline Latency
5 Cycles
CMOS OUTPUT MODE
tD ENC to DATA Delay
tC ENC to CLKOUT Delay
(Note 7)
(Note 7)
l1
l1
1.7 2.8
1.7 2.8
ns
ns
224012fb
5
5 Page 
FUNCTIONAL BLOCK DIAGRAM
LTC2240-12
AIN+
www.datasheet4u.com
INPUT
AIN– S/H
VCM
2.2μF
1.25V
REFERENCE
RANGE
SELECT
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
VDD
GND
SHIFT REGISTER
AND CORRECTION
SENSE
REF
BUF
REFH
REFL INTERNAL CLOCK SIGNALS
DIFFERENTIAL
DIFF
REF
AMP
INPUT
LOW JITTER
CLOCK
CONTROL
LOGIC
DRIVER
REFLB REFHA
2.2μF
0.1μF
1μF
REFLA REFHB
0.1μF ENC+
1μF
ENC–
M0DE LVDS SHDN OE
Figure 1. Functional Block Diagram
OUTPUT
DRIVERS
OVDD
+
+–
–
OF
D11
•
•
•
+
–+
–
D0
CLKOUT
OGND
224012 F01
224012fb
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC2240-12.PDF ] | |
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