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PDF LTC2245 Data sheet ( Hoja de datos )
| Número de pieza | LTC2245 | |
| Descripción | 10Msps Low Power 3V ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
www.datasheet4u.com
■ Sample Rate: 10Msps
■ Single 3V Supply (2.7V to 3.4V)
■ Low Power: 60mW
■ 74.4dB SNR
■ 90dB SFDR
■ No Missing Codes
■ Flexible Input: 1VP-P to 2VP-P Range
■ 575MHz Full Power Bandwidth S/H
■ Clock Duty Cycle Stabilizer
■ Shutdown and Nap Modes
■ Pin Compatible Family
125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit)
105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit)
80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit)
65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit)
40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit)
25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit)
10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit)
■ 32-Pin (5mm × 5Umm) QFN Package
APPLICATIO S
■ Wireless and Wired Broadband Communication
■ Imaging Systems
■ Spectral Analysis
■ Portable Instrumentation
LTC2245
14-Bit, 10Msps
Low Power 3V ADC
DESCRIPTIO
The LTC®2245 is a 14-bit 10Msps, low power 3V A/D
converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2245 is perfect for de-
manding imaging and communications applications with
AC performance that includes 74.4dB SNR and 90dB
SFDR for signals well beyond the Nyquist frequency.
DC specs include ±1LSB INL (typ), ±0.5LSB DNL (typ) and
no missing codes over temperature. The transition noise
is a low 1LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
REFH
REFL
FLEXIBLE
REFERENCE
ANALOG
INPUT
+
INPUT
S/H
–
14-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
CLOCK/DUTY
CYCLE
CONTROL
CLK
OUTPUT
DRIVERS
OVDD
D13
•
•
•
D0
OGND
2245 TA01
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
Typical INL, 2V Range
4096
8192
CODE
12288 16384
2245 G01
2245fa
1
1 page  
LTC2245
WU
TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
wwwf.sdatasheet4Sua.cmopmling Frequency
tL CLK Low Time
tH CLK High Time
tAP
tD
Pipeline
Latency
Sample-and-Hold Aperture Delay
CLK to DATA delay
Data Access Time After OE↓
BUS Relinquish Time
CONDITIONS
(Note 9)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
CL = 5pF (Note 7)
CL = 5pF (Note 7)
(Note 7)
MIN TYP MAX
●1
10
● 40
●5
50 500
50 500
UNITS
MHz
ns
ns
● 40
●5
50 500
50 500
ns
ns
0 ns
● 1.4 2.7 5.4
ns
●
4.3 10
ns
●
3.3 8.5
ns
5 Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 10MHz, input range = 2VP-P with differential
drive, unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and
11 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 10MHz, input range = 1VP-P with
differential drive.
Note 9: Recommended operating conditions.
TYPICAL PERFOR A CE CHARACTERISTICS
Typical INL, 2V Range
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
4096
8192
CODE
12288 16384
2245 G01
Typical DNL, 2V Range
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
4096 8192 12288 16384
CODE
2245 G02
8192 Point FFT, fIN = 5.1MHz,
–1dB, 2V Range
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
01234
FREQUENCY (MHz)
5
2245 G03
2245fa
5
5 Page 
LTC2245
APPLICATIO S I FOR ATIO
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
wwwc.daaptaaschietoetr4su.sctoimll hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, AIN+
should be driven with the input signal and AIN– should be
connected to VCMor a low noise reference voltage between
0.5V and 1.5V.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.5V. The VCM output pin (Pin
31) may be used to provide the common mode bias level.
VCM can be tied directly to the center tap of a transformer
to set the DC input level or as a reference level to an op amp
differential driver circuit. The VCM pin must be bypassed to
ground close to the ADC with a 2.2µF or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2245 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and reactance can
influence SFDR. At the falling edge of CLK, the sample-
and-hold circuit will connect the 4pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when CLK rises, holding the sampled input on
the sampling capacitor. Ideally the input circuitry should
be fast enough to fully charge the sampling capacitor
during the sampling period 1/(2FENCODE); however, this is
not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2245 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Terminating on the trans-
former secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen by
the ADC does not exceed 100Ω for each ADC input. A
disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
0.1µF T1
ANALOG
1:1
INPUT
25Ω
25Ω 0.1µF
25Ω
T1 = MA/COM ETC1-1T 25Ω
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
VCM
2.2µF
AIN+
LTC2245
12pF
AIN–
2245 F03
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
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| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC2245.PDF ] | |
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