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PDF LTC2242-12 Data sheet ( Hoja de datos )
| Número de pieza | LTC2242-12 | |
| Descripción | 250Msps ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC2242-12
12-Bit, 250Msps ADC
FEATURES
www■.datSaashmeept4leu.cRoamte: 250Msps
■ 65.4dB SNR
■ 78dB SFDR
■ 1.2GHz Full Power Bandwidth S/H
■ Single 2.5V Supply
■ Low Power Dissipation: 740mW
■ LVDS, CMOS, or Demultiplexed CMOS Outputs
■ Selectable Input Ranges: ±0.5V or ±1V
■ No Missing Codes
■ Optional Clock Duty Cycle Stabilizer
■ Shutdown and Nap Modes
■ Data Ready Output Clock
■ Pin Compatible Family
250Msps: LTC2242-12 (12-Bit), LTC2242-10 (10-Bit)
210Msps: LTC2241-12 (12-Bit), LTC2241-10 (10-Bit)
170Msps: LTC2240-12 (12-Bit), LTC2240-10 (10-Bit)
185Msps: LTC2220-1 (12-Bit)*
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)*
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)*
■ 64-Pin 9mm × 9mm QFN Package
U
APPLICATIO S
■ Wireless and Wired Broadband Communication
■ Cable Head-End Systems
■ Power Amplifier Linearization
■ Communications Test Equipment
DESCRIPTIO
The LTC®2242-12 is a 250Msps, sampling 12-bit A/D
converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2242-12 is perfect for
demanding communications applications with AC perfor-
mance that includes 65.4dB SNR and 78dB SFDR. Ultralow
jitter of 95fsRMS allows IF undersampling with excellent
noise performance.
DC specs include ±1.0LSB INL (typ), ±0.4LSB DNL (typ)
and no missing codes over temperature.
The digital outputs can be either differential LVDS, or
single-ended CMOS. There are three format options for
the CMOS outputs: a single bus running at the full data rate
or two demultiplexed buses running at half data rate with
either interleaved or simultaneous update. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 2.625V.
The ENC+ and ENC– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance over a wide range of clock duty cycles.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
*LTC2220-1, LTC2220, LTC2221, LTC2230, LTC2231 are 3.3V parts.
TYPICAL APPLICATIO
REFH
REFL
FLEXIBLE
REFERENCE
2.5V
VDD
ANALOG
INPUT
+
INPUT
S/H
–
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
CLOCK/DUTY
CYCLE
CONTROL
ENCODE
INPUT
OUTPUT
DRIVERS
0.5V
TO 2.625V
OVDD
D11
• CMOS
• OR
• LVDS
D0
OGND
224212 TA01
SFDR vs Input Frequency
85
80
75
70
1V RANGE
65
60
2V RANGE
55
50
45
40
0 100 200 300 400 500 600 700 800 900 1000
INPUT FREQUENCY (MHz)
224212 G11
224212f
1
1 page  
LTC2242-12
POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
wwwV.dDaDtasheet4u.Acnoamlog Supply Voltage
PSLEEP
Sleep Mode Power
PNAP Nap Mode Power
LVDS OUTPUT MODE
(Note 8)
SHDN = High, OE = High, No CLK
SHDN = High, OE = Low, No CLK
● 2.375 2.5 2.625
1
28
V
mW
mW
OVDD
Output Supply Voltage
IVDD Analog Supply Current
IOVDD
Output Supply Current
PDISS
Power Dissipation
CMOS OUTPUT MODE
(Note 8)
● 2.375 2.5 2.625
● 285 320
● 58 70
● 858 975
V
mA
mA
mW
OVDD
IVDD
PDISS
Output Supply Voltage
Analog Supply Current
Power Dissipation
(Note 8)
(Note 7)
● 0.5
●
2.5 2.625
285 320
740
V
mA
mW
WU
TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
fS Sampling Frequency
tL ENC Low Time (Note 7)
(Note 8)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
●1
250 MHz
● 1.9 2 500
● 1.5 2 500
ns
ns
tH ENC High Time (Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
● 1.9 2 500
● 1.5 2 500
ns
ns
tAP Sample-and-Hold Aperture Delay
0.4 ns
tOE Output Enable Delay
LVDS OUTPUT MODE
tD ENC to DATA Delay
tC ENC to CLKOUT Delay
DATA to CLKOUT Skew
Rise Time
Fall Time
Pipeline Latency
CMOS OUTPUT MODE
tD ENC to DATA Delay
tC ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline
Latency
Full Rate CMOS
Demuxed Interleaved
Demuxed Simultaneous
(Note 7)
(Note 7)
(Note 7)
(tC – tD) (Note 7)
(Note 7)
(Note 7)
(tC – tD) (Note 7)
●
5 10
ns
●1
●1
● –0.6
1.7
1.7
0
0.5
0.5
5
2.8 ns
2.8 ns
0.6 ns
ns
ns
Cycles
●1
●1
● –0.6
1.7
1.7
0
5
2.8
2.8
0.6
5
5 and 6
ns
ns
ns
Cycles
Cycles
Cycles
224212f
5
5 Page 
W
FUNCTIONAL BLOCK DIAGRA
AIN+
INPUT
www.datasAIhN–eet4u.cS/oHm
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
VCM
2.2µF
1.25V
REFERENCE
RANGE
SELECT
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
LTC2242-12
FIFTH PIPELINED
ADC STAGE
VDD
GND
SHIFT REGISTER
AND CORRECTION
SENSE
REF
BUF
REFH
REFL INTERNAL CLOCK SIGNALS
DIFFERENTIAL
DIFF
REF
AMP
INPUT
LOW JITTER
CLOCK
CONTROL
LOGIC
DRIVER
REFLB REFHA
2.2µF
0.1µF
1µF
REFLA REFHB
0.1µF ENC+
1µF
ENC–
M0DE LVDS SHDN OE
OUTPUT
DRIVERS
OVDD
+
+–
–
OF
D11
•
•
•
+
–+
–
D0
CLKOUT
OGND
224212 F01
Figure 1. Functional Block Diagram
224212f
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC2242-12.PDF ] | |
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