PDF CY7C1218F Data sheet ( Hoja de datos )

Número de pieza	CY7C1218F
Descripción	1-Mb (32K x36) Pipelined Sync SRAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com CY7C1218F 1-Mb (32K x36) Pipelined Sync SRAM Features • Registered inputs and outputs for pipelined operation • 32K × 36 common I/O architecture • 3.3V core power supply • 3.3V I/O operation • Fast clock-to-output times — 3.5 ns (for 166-MHz device) — 4.0 ns (for 133-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Offered in JEDEC-standard 100-pin TQFP package • “ZZ” Sleep Mode Option Functional Description[1] The CY7C1218F SRAM integrates 32,768 x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit Logic Block Diagram counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CCoEn1tr)o, ldeinppthu-tesxp(AanDsSioCn, Chip Enables ADSP, and (CE2 ADV), aWndriCteE3E),naBbulresst i(nBpWut[sA:Din]c, laundde BWE), and Global the Output Enable Write (GW). (OE) and the Asynchronous ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the Byte Write control inputs. GW when active LOW causes all bytes to be written. The CY7C1218F operates from a +3.3V core power supply while all outputs may operate with a +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. A0, A1, A MODE ADV CLK ADSC ADSP BWD BWC BWB BWA BWE GW CE1 CE2 CE3 OE ADDRESS REGISTER 2 A[1:0] Q1 BURST COUNTER CLR AND Q0 LOGIC DQD,DQD BYTE WRITE REGISTER DQC,DQPC BYTE WRITE REGISTER DQB,DQPB BYTE WRITE REGISTER DQA ,DQPA BYTE WRITE REGISTER ENABLE REGISTER PIPELINED ENABLE DQD ,DQPD BYTE WRITE DRIVER DQC ,DQPC BYTE WRITE DRIVER DQB,DQPB BYTE WRITE DRIVER DQA,DQPA BYTE WRITE DRIVER MEMORY ARRAY SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQPA DQPB DQPC DQPD INPUT REGISTERS ZZ 1 SLEEP CONTROL Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-05422 Rev. Revised January 26, 2004 1 page CY7C1218F Swiwnwg.lDeaWtaSrihteeeAt4cUc.ecosmses Initiated by ADSC ADSC Write accesses are initiated when the following condi- tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BW[A:D]) are asserted active to conduct a Write to the desired byte(s). ADSC-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global Write is conducted, the data presented to DQs is written into the corre- sponding address location in the memory core. If a Byte Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1218F is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. As a safety precaution, DQs are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1218F provides a two-bit wraparound counter, fed by A1, A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specif- ically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1, A0 00 Second Address A1, A0 01 Third Address A1, A0 10 01 00 11 10 11 00 11 10 01 Fourth Address A1, A0 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. remain inactive for CthEe1,dCurEa2ti,onCEo3f ,tZAZDRESCP,aaftnedr ADSC the ZZ must input returns LOW. ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Snooze mode standby current Device operation to ZZ ZZ recovery time ZZ Active to snooze current ZZ Inactive to exit snooze current Test Conditions ZZ > VDD – 0.2V ZZ > VDD – 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled Min. 2tCYC 0 Max. 40 2tCYC 2tCYC Unit mA ns ns ns ns Document #: 38-05422 Rev. Page 5 of 16 5 Page CY7C1218F Swwwwi.tDcahtaiSnhgeeWt4Ua.cvoemforms Read Cycle Timing[17] tCYC CLK ADSP ADSC ADDRESS GW, BWE, BW[A:D] CE ADV OE Data Out (Q) tCH tCL t ADS tADH tADS tADH tAS tAH A1 A2 tWES tWEH A3 Burst continued with new base address tCES tCEH Deselect cycle tADVS tADVH High-Z tCLZ tCO tOEHZ Q(A1) Single READ ADV suspends burst. tOEV tOELZ tCO tDOH Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) BURST READ tCHZ Q(A2) Q(A2 + 1) Burst wraps around to its initial state DON’T CARE UNDEFINED Note: 17. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document #: 38-05422 Rev. ** Page 11 of 16 11 Page

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