|
|
PDF CY7C1212F Data sheet ( Hoja de datos )
| Número de pieza | CY7C1212F | |
| Descripción | 1-Mbit (64K x 18) Pipelined Sync SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY7C1212F (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
CY7C1212F
1-Mbit (64K x 18) Pipelined Sync SRAM
Features
Functional Description[1]
• Registered inputs and outputs for pipelined operation
• 64K × 18 common I/O architecture
• 3.3V core power supply
• 3.3V I/O operation
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP package
• “ZZ” Sleep Mode Option
Logic Block Diagram
The CY7C1212F SRAM integrates 65,536 x 18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CCoEn1tr)o, ldeinppthu-tesxp(AanDsSioCn,
Chip Enables
ADSP, and
(CE2
ADV),
aWndriCteE3E),naBbulresst
i(nBpWut[sA:Bin],claundde
BWE), and Global
the Output Enable
Write (GW).
(OE) and the
Asynchronous
ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as
controlled by the Byte Write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1212F operates from a +3.3V core power supply
while all outputs may operate with a +3.3V supply. All inputs
and outputs are JEDEC-standard JESD8-5-compatible.
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ADDRESS
REGISTER
2 A[1:0]
BURST Q1
COUNTER
AND
CLR LOGIC Q0
DQB,DQPB
WRITE REGISTER
DQA,DQPA
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQB,DQPB
WRITE DRIVER
DQA,DQPA
WRITE DRIVER
MEMORY
ARRAY
SENSE OUTPUT
AMPS REGISTERS
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
INPUT
REGISTERS
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05423 Rev. *A
Revised April 7, 2004
1 page  
CY7C1212F
Swiwnwg.lDeaWtaSrihteeeAt4cUc.ecosmses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and
(4) the appropriate combination of the Write inputs (GW, BWE,
and BW[A:B]) are asserted active to conduct a Write to the
desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to DQs is written into the corre-
sponding address location in the memory core. If a Byte Write
is conducted, only the selected bytes are written. Bytes not
selected during a Byte Write operation will remain unaltered.
A synchronous self-timed Write mechanism has been
provided to simplify the Write operations.
Because the CY7C1212F is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQ inputs. Doing so will three-state the output drivers.
As a safety precaution, DQs are automatically three-stated
whenever a Write cycle is detected, regardless of the state of
OE.
Burst Sequences
The CY7C1212F provides a two-bit wraparound counter, fed
by A1, A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
00 01 10
01 00 11
10 11 00
11 10 01
Fourth
Address
A1, A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode.
remain inactive for
CthEe1,dCurEa2ti,onCEo3f ,tZAZDRESCP,aaftnedr
ADSC
the ZZ
must
input
returns LOW.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
2tCYC
0
Max.
40
2tCYC
2tCYC
Unit
mA
ns
ns
ns
ns
Document #: 38-05423 Rev. *A
Page 5 of 15
5 Page 
Swwwwi.tDcahtaiSnhgeeWt4Ua.cvoemforms (continued)
Write Cycle Timing[17, 18]
tCYC
CY7C1212F
CLK
ADSP
ADSC
ADDRESS
BWE,
BW[A :D]
GW
CE
tCH tCL
tADS tADH
tADS tADH
tAS tAH
A1 A2
Byte write signals are
ignored for first cycle when
ADSP initiates burst
tCES tCEH
ADV
OE
Data In (D)
Data Out (Q)
tDS tDH
High-Z
t
OEHZ
D(A1)
BURST READ
Single WRITE
D(A2)
tWES tWEH
ADSC extends burst
tADS tADH
A3
tWES tWEH
ADV suspends burst
t
ADVS
tADVH
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Note:
18. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A : B] LOW.
Document #: 38-05423 Rev. *A
Page 11 of 15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet CY7C1212F.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY7C1212F | 1-Mbit (64K x 18) Pipelined Sync SRAM | Cypress Semiconductor |
| CY7C1212H | 1-Mbit (64K x 18) Pipelined Sync SRAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |