PDF CY7C04312BV Data sheet ( Hoja de datos )

Número de pieza	CY7C04312BV
Descripción	(CY7C0431xBV) 10 Gb/s 3.3V QuadPort DSE Family
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com Features • QuadPort™ datapath switching element (DSE) family allows four independent ports of access for data path management and switching • High-bandwidth data throughput up to 10 Gb/s • 133-MHz[1] port speed x 18-bit-wide interface × 4 ports • High-speed clock to data access 4.2 ns (max.) • Synchronous pipelined devices — 1-Mb, ½-Mb, and ¼-Mb switch arrays — 64K/32K/16K × 18 device options • 0.25-micron CMOS for optimum speed/power • IEEE 1149.1 JTAG boundary scan • Width and depth expansion capabilities QuadPort DSE Family Applications CY7C0430BV CY7C04312BV CY7C04314BV 10 Gb/s 3.3V QuadPort™ DSE Family • BIST (Built-In Self-Test) controller • Dual Chip Enables on all ports for easy depth expansion • Separate upper-byte and lower-byte controls on all ports • Simple array partitioning (CY7C0430BV only) — Internal mask register controls counter wrap-around — Counter-Interrupt flags to indicate wrap-around — Counter and mask registers readback on address • 272-ball BGA package (27-mm × 27-mm × 1.27-mm ball pitch) • Commercial and industrial temperature ranges • 3.3V low operating power — Active = 750 mA (maximum) — Standby = 15 mA (maximum PORT 1 PORT 3 PORT 2 BUFFERED SWITCH PORT 4 PORT 2 PORT 1 PORT 3 PORT 4 REDUNDANT DATA MIRROR Note: 1. fMAX2 for commercial is 135 MHz and for industrial is 133 MHz. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-06027 Rev. A Revised May 14, 2002 1 page Pwwinw.CDaotanSfhiegeut4rUa.ctoiomn 272-ball Grid Array (BGA) Top View CY7C0430BV CY7C04312BV CY7C04314BV 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A LB I/O17 I/O15 I/O13 I/O11 I/O9 I/O16 I/O14 I/O12 I/O10 I/O10 I/O12 I/O14 I/O16 I/O9 I/O11 I/O13 I/O15 I/O17 LB P1 P2 P2 P2 P2 P2 P1 P1 P1 P1 P4 P4 P4 P4 P3 P3 P3 P3 P3 P4 B VDD1 UB I/O16 I/O14 I/O12 I/O10 I/O17 I/O13 I/O11 TMS TDI I/O11 I/O13 I/O17 I/O10 I/O12 I/O14 I/O16 UB VDD1 P1 P2 P2 P2 P2 P1 P1 P1 P4 P4 P4 P3 P3 P3 P3 P4 C A14 P1[9] A15 P1[8] CE1 P1 CE0 P1 R/W P1 I/O15 P1 VSS2 VSS2 I/O9 P1 TCK TDO I/O9 VSS2 VSS2 I/O15 R/W P4 P4 P4 CE0 P4 CE1 P4 A15 P4[8] A14 P4[9] D VSS1 A12 P1 A13 P1 OE VDD2 VSS2 VSS2 VDD2 VDD VSS VSS VDD VDD2 VSS2 VSS2 VDD2 OE A13 A12 VSS1 P1 P4 P4 P4 E A10 A11 MKRD CNTRD P1 P1 P1 P1[6] CNTRD MKRD P4 [6] P4 A11 P4 A10 P4 F A7 A8 A9 CNTINT P1 P1 P1 P1[7] CNTINT A9 A8 A7 P4[7] P4 P4 P4 G VSS1 A5 P1 A6 CNTINC P1 P1[6] CNTINC P4[6] A6 P4 A5 VSS1 P4 H A3 A4 MKLD CNTLD P1 P1 P1 P1[6] J VDD1 A1 P1 A2 VDD P1 K A0 INT CNTRST CLK P1 P1 P1[6] P1 L A0 INT CNTRST VSS P2 P2 P2[6] M VDD1 A1 P2 A2 CLK P2 P2 GND[5] GND[5] GND[5] GND[5] GND[5] GND[5] GND[5] GND[5] GND[5] GND[5] GND[5] GND[5] GND[5] GND[5] GND[5] GND[5] CNTLD MKLD P4[6] P4[6] A4 P4 A3 P4 VDD A2 P4 A1 VDD1 P4 CLK CNTRST P4 P4[6] INT P4 A0 P4 VSS CNTRST P3[6] INT P3 A0 P3 CLK P3 A2 P3 A1 VDD1 P3 N A3 A4 MKLD CNTLD P2 P2 P2 P2[6] CNTLD MKLD P3[6] P3[6] A4 P3 A3 P3 P VSS1 A5 P2 A6 CNTINC P2 P2[6] CNTINC P3[6] A6 P3 A5 VSS1 P3 R A7 A8 A9 CNTINT P2 P2 P2 P2[7] CNTINT A9 A8 A7 P3[7] P3 P3 P3 T A10 A11 MKRD CNTRD P2 P2 P2 P2[6] CNTRD MKRD P3[6] P3[6] A11 P3 A10 P3 U VSS1 A12 P2 A13 P2 OE VDD2 VSS2 VSS2 VDD2 VDD P2 VSS VSS VDD VDD2 VSS2 VSS2 VDD2 OE P3 A13 A12 VSS1 P3 P3 V A14 P2[9] A15 P2[8] CE1 P2 CE0 R/W I/O6 VSS2 VSS2 I/O0 P2 P2 P2 P2 NC NC I/O0 VSS2 VSS2 I/O6 R/W CE0 CE1 A15 A14 P3 P3 P3 P3 P3 P3[8] P3[9] W VDD1 UB P2 I/O7 I/O5 I/O3 I/O1 I/O8 I/O4 I/O2 MRST CLKBIST I/O2 I/O4 I/O8 I/O1 I/O3 I/O5 I/O7 P1 P1 P1 P1 P2 P2 P2 P3 P3 P3 P4 P4 P4 P4 UB VDD1 P3 Y LB I/O8 I/O6 I/O4 I/O2 I/O0 1/O7 I/O5 I/O3 I/O1 I/O1 I/O3 I/O5 I/O7 I/O0 I/O2 I/O4 I/O6 I/O8 LB P2 P1 P1 P1 P1 P1 P2 P2 P2 P2 P3 P3 P3 P3 P4 P4 P4 P4 P4 P3 Notes: 5. Central Leads are for thermal dissipation only. They are connected to device VSS. 6. Pin is VSS for CY7C04312BV and CY7C04314BV devices. 7. Pin is NC for CY7C04312BV and CY7C04314BV devices. 8. Pin is VSS for CY7C04312BV and CY7C04314BV devices. 9. Pin is VSS for CY7C04314BV devices. Document #: 38-06027 Rev. A Page 5 of 37 5 Page CY7C0430BV CY7C04312BV CY7C04314BV Swwwwi.tDcahtaiSnhgeeCt4Uh.acormacteristics Over the Industrial Operating Range (continued)[11] CY7C04312BV -133 -100 Parameter Description Min. Max. Min. Max. tSINT Clock to INT Set Time tRINT Clock to INT Reset Time tSCINT Clock to CNTINT Set Time tRCINT Clock to CNTINT Reset Time Master Reset Timing 1 7.5 1 10 1 7.5 1 10 1 7.5 1 10 1 7.5 1 10 tRS Master Reset Pulse Width 7.5 10 tRSR Master Reset Recovery Time 7.5 10 tROF Master Reset to Output Flags Reset Time 6.5 Port to Port Delays tCCS[11] Clock to Clock Set-up Time (time required after a write before you can read the same address location) 6.5 9 8 JTAG Timing and Switching Waveforms Parameter fJTAG tTCYC tTH tTL tTMSS tTMSH tTDIS tTDIH tTDOV tTDOX fBIST tBH tBL Description Maximum JTAG TAP Controller Frequency TCK Clock Cycle Time TCK Clock High Time TCK Clock Low Time TMS Set-up to TCK Clock Rise TMS Hold After TCK Clock Rise TDI Set-up to TCK Clock Rise TDI Hold after TCK Clock Rise TCK Clock Low to TDO Valid TCK Clock Low to TDO Invalid Maximum CLKBIST Frequency CLKBIST High Time CLKBIST Low Time CY7C043XXBV –133/–100 Min. Max. 10 100 40 40 20 20 20 20 20 0 50 6 6 Unit ns ns ns ns ns ns ns ns Unit MHz ns ns ns ns ns ns ns ns ns MHz ns ns Document #: 38-06027 Rev. *A Page 11 of 37 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
CY7C04312BV	(CY7C0431xBV) 10 Gb/s 3.3V QuadPort DSE Family	Cypress Semiconductor

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