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PDF CX25870 Data sheet ( Hoja de datos )

Número de pieza CX25870
Descripción (CX25870 / CX25871) Video Encoder
Fabricantes Conexant Systems 
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No Preview Available ! CX25870 Hoja de datos, Descripción, Manual

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CX25870/871
Video Encoder with Adaptive Flicker Filtering and HDTV Output
Conexant’s CX25870/871 is specifically designed to meet TV out system requirements
for the next-generation desktop PCs, notebook PCs, game consoles and set-top boxes.
With pin and software-forward compatibility to the Bt868/869, manufacturers can
quickly bring to market new solutions that support adaptive flicker filtering, ATSC
High-Definition Television (HDTV) output, and resolutions from 320 x 200 (minimum) to
1024 x 768 (maximum).
Adaptive flicker filtering is a Conexant technology in which the encoder looks at the
characteristics of the video content on a pixel-by-pixel basis and automatically
determines the optimal amount of flicker filtering required. If an end-user wants to work
on a spreadsheet while watching a DVD movie in a window, both the text-intensive
application requiring a lot of flicker filtering and the DVD movie requiring very little
flicker filtering can look their best. The amount of flicker filtering and overscan
compensation is entirely flexible.
The CX25870/871 also provides a 3-wire analog RGB or YPRPB HDTV output. While
the encoder is in HDTV output mode, the device will automatically insert horizontal
tri-level synchronization pulses and vertical synchronization broad pulses. The
CX25870/871 is compliant with the EIA770-3, SMPTE 274M/293M/296M standards and
supports ATSC HDTV resolutions including 480p, 720p, and 1080i.
All worldwide standard definition outputs are supported, including NTSC-M (N.
America, Taiwan), NTSC-J (Japan), PAL-B,D,G,H,I (Europe, Asia), PAL-M (Brazil), PAL-N
(Uruguay, Paraguay), PAL-Nc (Argentina), PAL-60 (China) and SECAM. The CX25870
and CX25871 are functionally identical, except the CX25871 can output standard
definition video with Macrovision Level 7.1.L1 copy protection capability.
Functional Block Diagram
24
P[23:0]
Input
DEMUX
HSYNC*
VSYNC*
BLANK*
FIELD
SIC
SID
ALTADDR
Timing
Serial
Interface
RESET*
SLEEP
SLAVE
PAL
XTALIN
XTALOUT
XTAL
OSC
Color
Space
Conversion
#1
Flicker
Filter/
Scaler
FIFO
Internal
Reference
Video
Encoder
Color
Space
Conversion
#2
To Internal
Clocks
DAC
MUX
PLL
Clock
Generation
10-Bit
10-Bit
10-Bit
10-Bit
BIAS
GEN
XTL_BFO
FSADJUST
COMP
VREF
DACA
DACB
DACC
DACD
VBIAS
CLKO
CLKI
Distinguishing Features
• HDTV Output Mode (patents pending)
– Compliant with EIA770-3 and
SMPTE274M/293M/296M
standards
– Automatic tri-level sync generation
– Component (YPRPB) or RGB HDTV
outputs
– Direct YPRPB or RGB output from
progressive RGB graphics video in
1080i, 720p, 480p ATSC
resolutions
• Software and register
forward-compatibility with the
Bt868/869
• Ability to accept many different input
data formats:
– 15/16/24-bit RGB multiplexed or
nonmultiplexed
– 16-bit 4:2:2 and 24-bit 4:4:4 YCrCb
multiplexed or nonmultiplexed
– Flexible pixel ordering with various
alternate formats
• Worldwide video output support:
NTSC-M, J, 4.43, PAL-B, D, G, H, I, M,
N, Nc, 60, and SECAM
• Interlaced and noninterlaced outputs
• S-Video output (simultaneous with
composite NTSC, PAL, or SECAM)
• SCART RGB or Y/C output for Europe
– 4th DAC is composite video
EN50-049 and IEC 933-1 compliant
• 5-Line vertical filtering scaling for
overscan compensation and flicker
reduction
• Adaptive Flicker Filtering for enhanced
image and peaking filters for text
sharpness (patents pending)
• CCIR601/ITU-RBT.601 (i.e., 480i) and
CCIR656 compatible input modes
• Luma and chroma comb filtering
• 4 x 10-bit DACs
• Programmable power management
• Master, pseudo-master or slave timing
operation
• Auto detection of TV
• 44 autoconfiguration modes
• Wide-Screen Signaling (WSS) support
for variable clock rates
– Adheres to EIAJ CPR-1024 and
ITU-R TST.1119-1 standards
• Full register set readback capability
• 3.3 V operation with scalable low
voltage graphic controller interface
from 1.8 V to 1.1 V
• Buffered crystal clock output pin
• Component YUV analog output
• Colorstream TM (EIA 770.2) and Super
Colorstream TM component video
outputs
• Macrovision 7.1.L1 copy protection
(CX25871)
• Compact 80-pin PQFP package
Data Sheet
100381B
September 2001

1 page




CX25870 pdf
www.DataSheet4U.com
Table of Contents
List of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 GUI Controller Programmability and Frequency Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.3 Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.3.2 Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.3.3 Low Voltage Graphics Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.3.4 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.3.5 Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.3.6 Clocking and Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.3.6.1 3:2 Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.3.7 Master, Pseudo-Master, and Slave Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1.3.7.1 Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1.3.7.2 Reason for BLANK* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
1.3.7.3 Pseudo-Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
1.3.7.4 Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
1.3.7.5 Slave Interface Without a Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
1.3.8 Autoconfiguration and Interface Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
1.3.9 Adaptations for Clock-Limited Master Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
1.3.10 Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
1.3.11 Input Pixel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27
1.3.12 YCrCb Inputs (For Standard TV Outputs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27
1.3.13 RGB Inputs (For Standard TV Outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29
1.3.14 Input Pixel Horizontal Sync. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29
1.3.15 Input Pixel Vertical Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30
1.3.16 Input Pixel Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30
1.3.17 Overscan Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31
1.3.18 Standard Flicker Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35
1.3.19 Adaptive Flicker Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36
1.3.20 VGA Registers Involved in the TV Out Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39
1.3.21 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40
100381B
Conexant
v

5 Page





CX25870 arduino
CX25870/871
Flicker-Free Video Encoder with Ultrascale Technology
List of Figures
Figure A-5.
www.DataSheet4U.com
Figure A-6.
Figure A-7.
Figure A-8.
Figure E-1.
Figure E-2.
Figure E-3.
Figure E-4.
Figure E-5.
Figure E-6.
Figure E-7.
Figure E-8.
Allowable Overscan Compensation Ratios for Dual Display, 800x600 Input, NTSC Output in 3:2
Clocking Mode A-8
Allowable Overscan Compensation Ratios for Dual Display, 800x600 Input, PAL-BDGHI Output
in 3:2 Clocking Mode A-9
Allowable Overscan Compensation Ratios for Dual Display, 1024x768 Input, NTSC Output . . .
A-10
Allowable Overscan Compensation Ratios for Dual Display, 1024x768 Input, PAL-BDGHI Out-
put A-11
CX25870/871’s Pseudo-Master Interface with a Graphics Controller as the Timing Master E-2
CX25870/871’s Slave Interface with a Graphics Controller as the Timing Master . . . . . . . . E-2
Typical Trilevel Sync Provided by CX25870/871 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-7
Proper Interface Timing Between the HDTV Source Device (Master) and CX25870/871 (Timing
Slave): Active Line in 1080i and 720p ATSC Format (RASTER_SEL[1:0] = 11 or 10), for R, G,
B, and Y Analog Outputs E-12
Proper Interface Timing Between the HDTV Source Device (Master) and CX25870/871 (Timing
Slave): Active Line in 1080i and 720p ATSC Format (RASTER_SEL[1:0] = 11 or 10) for P8 and
PR Analog Outputs E-13
Proper Interface Timing Between the HDTV Source Device (Master) and CX25870/871 (Timing
Slave): Broad Pulse Line in 1080i ATSC Format (RASTER_SEL[1:0] = 11) – Odd Field E-14
Proper Interface Timing Between the HDTV Source Device (Master) and CX25870/871 (Timing
Slave): Two Successive Active Fields in 1080i ATSC Format (RASTER_SEL[1:0] = 11) E-15
Proper Interface Timing Between the HDTV Source Device (Master) and CX25870/871 (Timing
Slave): Broad Pulse Line in 720p ATSC Format (RASTER_SEL[1:0] = 10) E-16
100381B
Conexant
xi

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