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Número de pieza MC68EC060
Descripción User Manual
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M68060 User’s Manual
Including the
MC68060,
MC68LC060,
and
MC68EC060
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different
applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not
convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola
product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims,
costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
µunintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are
registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
© MOTOROLA, 1994

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MC68EC060 pdf
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MC68060 ACRONYM LIST
AGU—address generation unit
ALU—arithmetic logic unit
ATC—address translation cache
BUSCR—bus control register
CACR—cache control register
CCR—condition code register
CM—cache mode
CPU—central processing unit
DFC—destination function code
DTTx—data transparent translation register
DRAM—dynamic random access memory
FPIAR—floating-point instruction address register
FPCR—floating-point control register
FPSP—floating-point software package
FPSR—floating-point status register
FPU—floating-point unit
FP7–FP0—floating-point data registers 7–0
FSLW—fault status long word
IEE—integer execute unit
IFP—instruction fetch pipeline
IFU—instruction fetch unit
IPU—instruction pipe unit
ISP—interrupt stack pointer
ITTR—instruction transparent translation register
IU—integer unit
JTAG—Joint Test Action Group
MMU—memory management unit
MOTOROLA
M68060 USER’S MANUAL
vii

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MC68EC060 arduino
Table of Contents
www6..D1a.t3aS.h4eet4U.com Accrued Exception Byte ........................................................................... 6-6
6.1.4
Floating-Point Instruction Address Register (FPIAR) ................................. 6-7
6.2 Floating-Point Data Formats and Data Types............................................... 6-7
6.3 Computational Accuracy ............................................................................. 6-11
6.3.1
Intermediate Result................................................................................... 6-12
6.3.2
Rounding the Result ................................................................................. 6-13
6.4 Postprocessing Operation........................................................................... 6-15
6.4.1
Underflow, Round, and Overflow.............................................................. 6-15
6.4.2
Conditional Testing ................................................................................... 6-16
6.5 Floating-Point Exceptions ........................................................................... 6-19
6.5.1
Unimplemented Floating-Point Instructions .............................................. 6-19
6.5.2
Unsupported Floating-Point Data Types................................................... 6-21
6.5.3
Unimplemented Effective Address Exception........................................... 6-22
6.6 Floating-Point Arithmetic Exceptions .......................................................... 6-22
6.6.1
Branch/Set on Unordered (BSUN)............................................................ 6-24
6.6.1.1
Trap Disabled Results (FPCR BSUN Bit Cleared) ................................. 6-24
6.6.1.2
Trap Enabled Results (FPCR BSUN Bit Set) ......................................... 6-24
6.6.2
Signaling Not-a-Number (SNAN) .............................................................. 6-25
6.6.2.1
Trap Disabled Results (FPCR SNAN Bit Cleared) ................................. 6-25
6.6.2.2
Trap Enabled Results (FPCR SNAN Bit Set) ......................................... 6-26
6.6.3
Operand Error........................................................................................... 6-26
6.6.3.1
Trap Disabled Results (FPCR OPERR Bit Cleared)............................... 6-27
6.6.3.2
Trap Enabled Results (FPCR OPERR Bit Set)....................................... 6-27
6.6.4
Overflow.................................................................................................... 6-28
6.6.4.1
Trap Disabled Results (FPCR OVFL Bit Cleared) .................................. 6-29
6.6.4.2
Trap Enabled Results (FPCR OVFL Bit Set) .......................................... 6-29
6.6.5
Underflow.................................................................................................. 6-30
6.6.5.1
Trap Disabled Results (FPCR UNFL Bit Cleared) .................................. 6-31
6.6.5.2
Trap Enabled Results (FPCR UNFL Bit Set) .......................................... 6-31
6.6.6
Divide-by-Zero .......................................................................................... 6-32
6.6.6.1
Trap Disabled Results (FPCR DZ Bit Cleared)....................................... 6-33
6.6.6.2
Trap Enabled Results (FPCR DZ Bit Set)............................................... 6-33
6.6.7
Inexact Result ........................................................................................... 6-33
6.6.7.1
Trap Disabled Results (FPCR INEX1 Bit and INEX2 Bit Cleared........... 6-34
6.6.7.2
Trap Enabled Results (Either FPCR INEX1 Bit or INEX2 Bit Set).......... 6-34
6.7 Floating-Point State Frames ....................................................................... 6-35
Section 7
Bus Operation
7.1 Bus Characteristics ....................................................................................... 7-1
7.2 Full-, Half-, and Quarter-Speed Bus Operation and BCLK ........................... 7-3
7.3 Acknowledge Termination Ignore State Capability ....................................... 7-4
7.4 Bus Control Register..................................................................................... 7-4
7.5 Data Transfer Mechanism............................................................................. 7-5
7.6 Misaligned Operands .................................................................................... 7-9
MOTOROLA
M68060 USER’S MANUAL
xiii

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