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PDF MC68EC040V Data sheet ( Hoja de datos )
| Número de pieza | MC68EC040V | |
| Descripción | Microprocessor | |
| Fabricantes | Motorola Semiconductor | |
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om REV2.2 (11/02/99)
taSheet4U.cAPPENDIX B
aMC68EC040
ww.D NOTE
w Rev. 2.2 contains timing information for 40 MHz operation.
mRefer to chang bars. Some TBD values will be filled in shortly.
oAll references to MC68EC040 also apply to the MC68EC040V.
.cRefer to Appendix C MC68040V and MC68EC040V for more
information on the MC68EC040V.
UThe MC68EC040 is Motorola's third generation of M68000-compatible, high-performance,
32-bit microprocessors. The MC68EC040 is an embedded controller employing a highly
t4integrated architecture to provide very high performance in a monolithic HCMOS device.The
MC68EC040 integrates an MC68040-compatible integer unit, an access control unit (ACU),
eand independent 4-Kbyte instruction and data caches. A six-stage instruction pipeline, mul-
tiple internal buses, and a full internal Harvard architecture, including separate caches for
eboth instruction and data accesses, provides a high degree of instruction execution parallel-
hism. The inclusion of on-chip bus snooping logic, which directly supports cache coherency
in multimaster applications, enhances cache functionality.
SThe MC68EC040 is user-object-code compatible with previous members of the M68000
tafamily and is specifically optimized to reduce the execution time of compiler-generated code.
The MC68EC040 is pin compatible with the MC68040 and MC68LC040. The MC68EC040
ais implemented in Motorola's latest HCMOS technology, providing an ideal balance between
speed, power, and physical device size. Figure B-1 provides a simplified block diagram of
.Dthe MC68EC040.
The main features of the MC68EC040 include:
w• MC68040-Compatible Integer Execution Unit
• 4-Kbyte Instruction Cache and 4-Kbyte Data Cache Accessible Simultaneously
w• 32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Bursting
w mInterface
.co• User-Object-Code Compatible with All M68000 Microprocessors
U• Concurrent Integer Unit, ACU, and Bus Controller Operation Maximizes Throughput
t4• Low-Latency Bus Accesses for Reduced Cache-Miss Penalty
ee• Multimaster/Multiprocessor Support via Bus Snooping
Sh• 4-Gbyte Direct Addressing Range
www.DataMOTOROLA
M68040 USER’S MANUAL
B-1
1 page  
MC68EC040 REV2.2 (11/02/99)
control applications while maintaining cache integrity. Refer to Section 4 Instruction and
Data Caches for details concerning cachability. Figure B-4 illustrates the ACR format.
31
24 23
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOGICAL ADDRESS BASE LOGICAL ADDRESS MASK E S 0 0 0 U1 U0 0 CM 0 0 W 0 0
Figure B-4. MC68EC040 Access Control Register Format
ADDRESS BASE
This 8-bit field is compared with physical address bits A31–A24. Addresses that match in
this comparison (and are otherwise eligible) are accessible.
ADDRESS MASK
This 8-bit field contains a mask for the ADDRESS BASE field. Setting a bit in the AD-
DRESS MASK field causes the processor to ignore the corresponding bit in the AD-
DRESS BASE field. Setting some of the ADDRESS MASK bits to ones obtains blocks of
memory larger than 16 Mbytes. The low-order bits of this field are normally set to define
contiguous blocks larger than 16 Mbytes, although contiguous blocks are not required.
E—Enable
This bit enables and disables transparent translation of the block defined by this register.
Refer to Section 3 Memory Management Unit (Except MC68EC040 and
MC68EC040V) for details on transparent translation.
0 = Access control disabled.
1 = Access control enabled.
S—Supervisor/User Mode
This field specifies the way FC2 is used in matching an address:
00 =Match only if FC2 = 0 (user mode access).
01 =Match only if FC2 = 1 (supervisor mode access).
10, 11 =Ignore FC2 when matching.
U1, U0—User Page Attributes
These two bits drive on the user page attribute signals (UPA1 and UPA0). If an external
bus transfer results from the access, U0 and U1 are echoed to the UPA0 and UPA1
signals, respectively. The user can program these bits to support extended addressing,
bus snooping, or other applications. The MC68EC040 does not interpret these bits.
MOTOROLA
M68040 USER’S MANUAL
B-5
5 Page 
MC68EC040 REV2.2 (11/02/99)
status register and translation control register of the MC68040. The MMU status register
opcode of the MOVEC instruction can modify the ACU status register. The MC68EC040
ACU status register does not provide additional functionality to the ACU and is only provided
for compatibility with the ACU MC68EC030 status register. The ACU status register may not
be implemented in future M68EC0X0 products.
B.7 MC68EC040 ELECTRICAL CHARACTERISTICS
The following paragraphs provide information on the maximum rating and thermal charac-
teristics for the MC68EC040 only. Refer to Appendix C MC68040V and MC68EC040V for
more information on electrical characteristics for the MC68EC040V. This section is subject
to change. For the most recent specifications, contact a Motorola sales office or complete
the registration card at the end of this manual.
B.7.1 Maximum Ratings
Characteristic
Supply Voltage
Input Voltage
Maximum Operating Junction Temperature
Minimum Operating Ambient Temperature
Storage Temperature Range
Table 12-2.
Symbol
VCC
Vin
TJ
TA
Tstg
Value
–0.3 to +7.0
–0.5 to +7.0
110
0
–55 to 150
Unit This device contains protective
circuitry against damage due to
V high static voltages or electrical
fields; however, it is advised that
V
normal precautions be taken to
avoid application of any voltages
°C
higher than maximum-rated
voltages to this high-impedance
circuit. Reliablity of operation is
°C enhanced if unused inputs are
tied to an appropriate logic
°C
voltage level (e.g., either GND or
VCC).
B.7.2 Thermal Characteristics
Characteristic
Thermal Resistance, Junction to Case—
PGA Package
Symbol
θJC
Value
3
Rating
°C/W
MOTOROLA
M68040 USER’S MANUAL
B-11
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