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PDF TMP86FM25F Data sheet ( Hoja de datos )
| Número de pieza | TMP86FM25F | |
| Descripción | 8-Bit Microcontroller | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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wwCwo.mDaptaaSrhiseoent4Uta.cbolme of TMP86CM25F/CS25F/PS25F/C925XB and TMP86CM25AF/FM25F
Difference
TMP86CM25F/
TMP86CS25F
TMP86PS25F
TMP86C925XB
(Emulation chip)
TMP86FM25F
TMP86CM25AF
ROM
RAM
I/O
External
Interrupt
AD Converter
Timer Counter
Serial Interface
LCD
Key-on
Wakeup
Operating
Voltage
in MCU Mode
Operating
Temperature
in MCU Mode
Writing to
Flash Memory
Package
CPU Wait (Note 1)
32 K (Mask ROM)
60 K (Mask ROM)
2K
42 pin
60 K (OTP)
−
−
42 pin (MCU part)
5 pin
8-bit AD converter × 8 ch
18-bit timer × 1 ch
8-bit timer × 4 ch
8-bit SIO × 2 ch
UART × 1 ch
60 seg × 16 com
4 ch
1.8 to 5.5 V at 4.2 MHz
2.7 to 5.5 V at 8 MHz
4.5 to 5.5 V at 16 MHz
1.8 to 5.25 V at 4.2 MHz
2.7 to 5.25 V at 8 MHz
4.5 to 5.25 V at 16 MHz
32 K (Flash)
32 K (Mask ROM)
2K
42 pin
5 pin
8-bit AD converter × 8 ch (Note 3)
18-bit timer × 1 ch
8-bit timer × 4 ch
8-bit SIO × 2 ch
UART × 1 ch
60 seg × 16 com (Note 4)
4 ch
1.8 to 3.6 V at 4.2 MHz (External clock)
1.8 to 3.6 V at 8 MHz (Resonator)
2.7 to 3.6 V at 16 MHz
−40 to 85℃
0 to 60°C
−40 to 85°C
−
P-QFP100-1420-0.65A
N/A
FBGA272
2.7 to 3.6V at 16 MHz
25°C ± 5°C
−
P-QFP100-1420-0.65A
Available (Note 2)
Note 1: The CPU wait is a CPU halt function for stabilizing of power supply of Flash memory. The CPU wait
period is as follows. In the CPU wait period except RESET, CPU is halted but peripheral functions
are not halted. Therefore, if the interrupt occurs during the CPU wait period, the interrupt latch is set.
In this case, if the IMF has been set to “1”, the interrupt service routine is executed after CPU wait
period. For details refer to 1.1 “Flash Memory” in TMP86FM25F data sheet.
Condition
After reset release
Changing from STOP mode to NORMAL mode
(at EEPCR<MNPWDW> = “1”)
Changing from STOP mode to SLOW mode
(at EEPCR<MNPWDW> = “1”)
Changing from IDLE0/1/2 mode to NORMAL mode
(at EEPCR<ATPWDW> = “0”)
Changing from SLEEP0/1/2 mode to SLOW mode
(at EEPCR<ATPWDW> = “0”)
Wait Time
210/fc[s]
210/fc[s]
23/fs[s]
210/fc[s]
23/fs[s]
Halt/Operate
CPU Peripherals
Halt Halt
Halt Operate
Halt Operate
Halt Operate
Halt Operate
Note 2: Though the TMP86CM25AF does not have a Flash memory, the CPU wait function is inserted in
TMP86CM25A to keep the compatibility with Flash product (TMP86FM25F).
Note 3: AD conversion time of TMP86CM25A/FM25 is different from that of TMP86CM25/CS25/PS25/C925.
For details, refer to 2.12 “8-Bit AD Converter (ADC)”.
Note 4: The reference voltage of TMP86CM25A/FM25 is different from that of TMP86CM25/CS25/
PS25/C925. For details, refer to “Electrical Characteristics”.
2004-03-01
1 page  
Under development
TMP86FM25
Pin Funtions
www.DataSThheeet4TUM.coPm86FM25 has MCU mode and serial PROM mode.
(1) MCU mode
In the MCU mode, the TMP86FM25 is a pin compatible with the TMP86CM25A (Make
sure to fix the TEST pin to low level).
(2) Serial PROM mode
In the Serial PROM mode, programming to Flash memory is available by executing BOOT
ROM.
In the serial PROM mode, TXD (P16) and RXD (P15) pins are used as a serial interface pin.
Therefore, if the programming is executed on-board after mounting, these pins should be
released from the other devices for communication in serial PROM mode.
86FM25-4
2004-03-01
5 Page 
Under development
TMP86FM25
FLASH Control Register
www.DataSheet4U.co7m
6
5
EEPCR
(0FE0H)
EEPMD
EEPMD
FLASH write enable control
(Write protect).
4 3 2 10
EEPRS ATPWDW MNPWDW (Initial value: 1100 *011)
1100: FLASH write disable.
0011: FLASH write enable.
Other values: Reserved.
Program Execution Area
RAM/
BOOT
FLASH
EEPRS
ATPWDW
MNPWDW
FLASH write forcible stop.
Automatic power control for the
FLASH control circuit in the
IDLE0/1/2, SLEEP0/1/2 modes.
(This bit is available only when
MNPWDW is set to “1”.)
Software-based power control
for the FLASH control circuit.
0: −
1: FLASH writing is forced to stop.
(The write data counter is initialized.)
* After writing “1” to EEPRS, it is
automatically cleared to “0”.
0: Automatic power shut down is executed in
IDLE0/1/2 and SLEEP0/1/2 modes.
1: Automatic power shut down is not executed
in IDLE0/1/2 and SLEEP0/1/2 modes. (The
power is always supplied in these modes.)
0: The power for the FLASH control circuit is
turned off.
1: The power for the FLASH control circuit is
turned on.
R/W
Read
only
R/W
Read
only
Note 1: The EEPMD, EEPRS, and MNPWDW can be rewritten only when a program fetch is taking place in the RAM or
BOOT-ROM area. If an attempt is made to rewrite the EEPCR register when a program is being executed in the
FLASH area, the EEPMD, EEPRS, and MNPWDW keep holding the previous data; they are not rewritten.
Note 2: To write to the FLASH, set the EEPMD with “0011B” in advance when a program fetch is taking place in the RAM
area.
Note 3: To forcibly stop writing of FLASH, set the EEPRS to “1” when a program fetch is taking place in the RAM area.
Note 4: The ATPWDW functions only if the MNPWDW is “1”. If the MNPWDW is “0”, the power for the FLASH control circuit is
kept turned off regardless of the setting of the ATPWDW.
Note 5: When a STOP mode is executed, the power for the FLASH control circuit is turned off regardless of the setting of the
ATPWDW. If the MNPWDW is “0”, entering/exiting the STOP mode allows the power for the FLASH control circuit to
be kept turned off.
Note 6: Executing a read instruction to the EEPCR register results in bit3 being read as undefined. Bit2 is always read as “0”.
Note 7: The following attention is necessary when the MNPWDW is set or cleared.
When the MNPWDW is
changed from “1” to “0”
When the MNPWDW is
changed from “0” to “1”
Clear the interrupt master enable flag (IMF) to “0” in advance to disable an
interrupt. After that, do not set IMF to “1” during EEPSR<EWUPEN> = “0”. If a
watchdog timer is in use, clear the binary counter for the watchdog timer just
before MNPWDW is changed from “1” to “0”.
When write to or read from the Flash area, make sure that the
EEPSR<EWUPEN> is “1” by software. Once the MNPWDW is rewritten from
“0” to “1” by software, keep performing software-based polling until the
EEPSR<EWUPEN> becomes “1”.
Note 8: In MCU mode, the EEPMD and EEPRS should be set to “1100B” and “0”.
Figure 1.2.2 FLASH Control Register
86FM25-10
2004-03-01
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TMP86FM25F.PDF ] | |
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