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PDF SH7729R Data sheet ( Hoja de datos )
| Número de pieza | SH7729R | |
| Descripción | 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SH7729R (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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32
SH7729R Group
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperH RISC engine Family/SH7700 Series
Rev.5.00
2003.9.19
1 page  
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
wwuswe.dDaatsaStehsetept4inUs.coormto reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note:
When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev. 5.0, 09/03, page v of xlvi
5 Page 
Section
5.5.1 Invalidating a
Specific Entry
Page
154
www.DataSheet4U.com
5.5.2 Invalidating a
Specific Address
155
5.5.3 Reading the
Data of a Specific Entry
7.2.6 Interrupt
171
Exception Handling and
Priority
Table 7.4 Interrupt
Exception Handling
Sources and Priority
(IRQ Mode)
7.3.6 Interrupt
Request Register 0
(IRR0)
182
Description
Description amended
A specific cache entry can be invalidated by accessing the allocated
memory cache and writing a 0 to the entry’s U and V bits. The A bit is
cleared to 0, and an address is specified for the entry address and the
way. If the U bit of the way of the entry in question was set to 1, the
entry is written back and the V and U bits specified by the write data are
written to.
In the following example, the write data is specified in R0 and the
address is specified in R1.
; R0 = H'0000 0000 LRU = H'000, U = 0, V = 0
; R1 = H'F000 1080, Way = 1, Entry = H'08, A = 0
;
MOV.L R0, @R1
To invalidate all entries and ways, write 0 to the following addresses.
Addresses
F000 0000
F000 0010
F000 0020
:
F000 3FF0
This involves a total of 1,024 writes.
The above operation should be performed using a non-cacheable area.
Newly added
Description amended
; R1=H'F100 004C; data array access, entry=H'04, Way = 0,
; longword address = 3
;
MOV.L @R0,R1 ; Longword 3 is read.
IPR (bit numbers) for SCI amended
(Before)IPRB(3-0) → (After)IPRB(7-4)
Description amended
When clearing an IRQ5R–IRQ0R bit to 0, read the bit while bit set
to 1, and then write 0. In this case, 0 should be written only to the
bits to be cleared and 1 to the other bits. The contents of the bits
to which 1 is written do not change.
9.2.1 Standby Control 230
Register (STBCR)
Description added
Bit 1—Module Standby 1 (MSTP1)
Before switching the RTC to module standby, access at least one
among the registers RTC, SCI, and TMU.
Rev. 5.0, 09/03, page xi of xlvi
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SH7729R.PDF ] | |
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