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PDF PLL520-28 Data sheet ( Hoja de datos )
| Número de pieza | PLL520-28 | |
| Descripción | (PLL520-2x) Low Phase Noise VCXO | |
| Fabricantes | PhaseLink Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PLL520-28 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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PLL520-28/-29
www.DataSheet4U.com Low Phase Noise VCXO (for 120-200MHz Fund Xtal)
FEATURES
• 120MHz to 200MHz Fundamental Mode Crystal.
• Output range: 120 – 200MHz (no PLL).
• Low Injection Power for crystal 50uW.
• Sub 0.5pS RMS phase jitter ( 12kHz to 20MHz ).
• PECL (PLL520-28) or LVDS output (PLL520-29).
• Integrated variable capacitors.
• Supports 2.5V or 3.3V-Power Supply.
• Available in 16-Pin (TSSOP or 3x3mm QFN).
DESCRIPTION
The PLL520-28/-29 are a family of VCXO IC’s
specifically designed to pull high frequency
fundamental crystals. They achieve very low current
into the crystal resulting in better overall stability.
Their internal varicaps allow an on chip frequency
pulling, controlled by the VCON input. Their very
low jitter makes them ideal for the most demanding
timing requirements.
BLOCK DIAGRAM
PIN CONFIGURATION
(Top View)
VDD
XIN
XOUT
N/C
N/C
OE
VCON
GND
1
2
3
4
5
6
7
8
16 N/C
15 N/C
14 GND
13 CLKC
12 VDD
11 CLKT
10 N/C
9 N/C
XIN
XOUT
N/C
OE
12 11 10 9
13 8
14 7
P520-2x
15 6
16 5
1234
GND
CLKC
VDD
CLKT
VCON Oscillator
Amplifier
XIN
w/
integrated
varicaps
XOUT
OE
Q
Q
PLL520-28/-29
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
PLL520-28
0 (Default) Output enabled
1 Tri-state
PLL520-29
0 Tri-state
1 (Default) Output enabled
OE input: Logical states defined by PECL levels for PLL520-28
Logical states defined by CMOS levels for PLL520-29
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1
1 page  
www.DataSheet4U.com
PLL520-28/-29
Low Phase Noise VCXO (for 120-200MHz Fund Xtal)
9. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
VOH
VOL
CONDITIONS
RL = 50 Ω to (VDD – 2V)
(see figure)
10. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
tr
tf
CONDITIONS
@20/80% - PECL
@80/20% - PECL
MIN.
VDD – 1.025
MAX.
VDD – 1.620
UNITS
V
V
MIN.
TYP.
0.6
0.5
MAX.
1.5
1.5
UNITS
ns
ns
PECL Levels Test Circuit
OUT
50Ω
VDD
2.0V
PECL Output Skew
OUT
50%
OUT
50Ω
OUT
80%
50%
20%
OUT
tR
OUT
tSKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PLL520-28.PDF ] | |
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