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PDF CY7C335 Data sheet ( Hoja de datos )
| Número de pieza | CY7C335 | |
| Descripción | Universal Synchronous EPLD | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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fax id: 60181CY7C335
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Features
• 100-MHz output registered operation
• Twelve I/O macrocells, each having:
— Registered, three-state I/O pins
— Input and output register clock select multiplexer
— Feed back multiplexer
— Output enable (OE) multiplexer
• Bypass on input and output registers
• All twelve macrocell state registers can be hidden
• User configurable I/O macrocells to implement JK or
RS flip-flops and T or D registers
• Input multiplexer per pair of I/O macrocells allows I/O
pin associated with a hidden macrocell state register
to be saved for use as an input
• Four dedicated hidden registers
• Twelve dedicated registered inputs with individually
programmable bypass option
• Three separate clocks—two input clocks, two output
clocks
• Common (pin 14-controlled) or product term-controlled
output enable for each I/O pin
• 256 product terms—32 per pair of macrocells, variable
distribution
• Global, synchronous, product term-controlled, state
register set and reset—inputs to product term are
clocked by input clock
Logic Block Diagram
OE/I11
I10
I9
I8
I7
I6
VSS
14 13 12 11 10
9
8
CY7C335
Universal Synchronous EPLD
— 2-ns input set-up and 9-ns output register clock to
output
— 10-ns input register clock to state register clock
• 28-pin, 300-mil DIP, LCC, PLCC
• Erasable and reprogrammable
• Programmable security bit
Functional Description
The CY7C335 is a high-performance, erasable, programma-
ble logic device (EPLD) whose architecture has been opti-
mized to enable the user to easily and efficiently construct very
high performance state machines.
The architecture of the CY7C335, consisting of the user-con-
figurable output macrocell, bidirectional I/O capability, input
registers, and three separate clocks, enables the user to de-
sign high-performance state machines that can communicate
either with each other or with microprocessors over bidirec-
tional parallel buses of user-definable widths.
The four clocks permit independent, synchronous state ma-
chines to be synchronized to each other.
The user-configurable macrocells enable the designer to des-
ignate JK-, RS-, T-, or D-type devices so that the number of
product terms required to implement the logic is minimized.
The CY7C335 is available in a wide variety of packages in-
cluding 28-pin, 300-mil plastic and ceramic DIPs, PLCCs, and
LCCs.
I5 I4 I3 I2 I1/CLK3 I0/CLK2 CLK1
76
54
32
1
9 19
11 17
PROGRAMMABLE AND ARRAY
(258x68)
13
15 13 17 11 19 15
13
17 11 19 9
15 16 17 18 19 20
I/O11
I/O10
I/O9
I/O8
I/O7
I/O6
21 22 23 24 25 26 27 28
VSS
VC C
I/O5 I/O4
I/O3 I/O2 I/O1 I/O0 C335–1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 1991 – Revised March 26, 1997
1 page  
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SET PRODUCT TERM
S
DQ
TO ARRAY
SCLK1
SCLK2
0
STATE
CLK
1 MUX
C5
RESET PRODUCT TERM
Q
R
Figure 3. CY7C335 Hidden Macrocell
C335–6
CY7C335
PIN 1
PIN 2
PIN 3
1
0 MUX
C9
0
1 MUX
C8
1
0 MUX
C10
SCLK2 TO OUTPUT MACROCELLS AND HIDDEN MACROCELLS
ICLK1 ICLK2
SCLK1 TO OUTPUT MACROCELLS AND HIDDEN
MACROCELLS
1 TO ARRAY
MUX
0
1
0 MUX
1
0 MUX
1
MUX
0
TO ARRAY
C335–7
Figure 4. CY7C335 Input Clocking Scheme
5
5 Page 
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Switching Waveform
INPUTOR
I/O PIN
INPUT REG.
CLOCK
tIS tIH
tWH
OUTPUT
REG. CLOCK
tICO
OUTPUT
tIOH
tPD
tICER
tER
PIN 14
AS OE
tWL
tCOS
tPXZ
Power-Up Reset Waveform[7]
90%
VCC
OUTPUT
CLOCK
tPOR
CY7C335
tS tH
tWH tWL
tCO
tOH
tEA
tICEA
tPZX
C335–20
tCOS
tWL
C335–21
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet CY7C335.PDF ] | |
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