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PDF CMS6416LAx-75xx Data sheet ( Hoja de datos )
| Número de pieza | CMS6416LAx-75xx | |
| Descripción | 64M(4Mx16) Low Power SDRAM | |
| Fabricantes | FIDELIX | |
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CMS6416LAx-75xx
64M(4Mx16) Low Power SDRAM
Rev1.3, Nov. 2005
Revision 1.3
November, 2005
1 page  
Pin Description
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CLK Input
CKE
Input
/CS
/CAS, /RAS, /WE
LDQM, UDQM
Input
Input
Input
BA0, BA1
Input
A0-A11
DQ
NC
VDDQ
VSSQ
VDD
VSS
Input
I/O
-
Supply
Supply
Supply
Supply
CMS6416LAx-75xx
Description
Clock : CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. Deactivating the
clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation(all banks idle),
ACTIVE POWER-DOWN(row active in any bank) or CLOCK SUSPEND operation(burst/access
in progress). CKE is synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers,
including CLK, are disabled during power-down and self refresh modes, providing low standby
power. CKE may be tied HIGH.
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when /CS is registered HIGH. /CS provides for external
bank selection on systems with multiple banks. /CS is considered part of the command code.
Command Inputs : /CAS, /RAS, and /WE (along with /CS) define the command being entered.
Input/Output Mask: L(U)DQM is sampled HIGH and is an input mask signal for write accesses
and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The
output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle.
LDQM corresponds to DQ0 – DQ7 and UDQM corresponds to DQ8–DQ15.
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied. These pins also provide the op-code during a LOAD
MODE REGISTER command.
Address Inputs: A0–A11 are sampled during the ACTIVE command (row-address A0–A11)
and READ/WRITE command (column-address A0–A7; with A10 defining auto precharge) to
select one location out of the memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank
selected by BA0, BA1 (A10 LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Data Input/Output : Data bus
No Connect
DQ Power: Provide isolated power to DQs for improved noise immunity.
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Power Supply: Voltage dependent on option.
Ground.
Rev1.3, Nov. 2005
5 Page 
CMS6416LAx-75xx
EXTENDED MODE REGISTER
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The Extended Mode Register controls additional functions such
as the Temperature Compensated Self Refresh (TCSR) Control,
Partial Array Self Refresh (PASR), and Output Drive
Strength.The Extended Mode Register is programmed via the
Mode Register Set command (BA1=1, BA0=0) and retains the
stored information until it is programmed again or the device
loses power. The Extended Mode Register must be
programmed with M8 through M11 set to “0”. The Extended
Mode Register must be loaded when all banks are idle and no
bursts are in progress, and the controller must wait the
specified time initiating any subsequent operation. Violating
either of these requirements results in unspecified operation.
AUTO TEMPERATURE COMPENSATED SELF REFRESH
Every cell in the DRAM requires refreshing due to the capacitor
losing its charge over time. The refresh rate is dependent on
temperature. At higher temperatures a capacitor loses charge
quicker than at lower temperatures, requiring the cells to be
refreshed more often. In order to save power consumption,
according to the temperature, Mobile-SDRAM includes the
internal temperature sensor and control units to control the self
refresh cycle automatically.
PARTIAL ARRAY SELF REFRESH
The Partial Array Self Refresh (PASR) feature allows the
controller to select the amount of memory that will be refreshed
during SELF REFRESH. The refresh options are all banks
(banks 0, 1, 2, and 3); two banks(banks 0 and 1 or 2 and 3 by
M7); and one bank (bank 0 or 2 by M7). WRITE and READ
commands occur to any bank selected during standard
operation, but only the selected banks in PASR will be
refreshed during SELF REFRESH. The data in banks 2 and 3
will be lost when the two bank option with M7=0 is used.
Similarly the data will be lost in banks 1, 2, and 3 when the one
bank option with M7=0 is used down .
Driver Strength Control
The driver strength feature allows one to reduce the drive
strength of the I/O’s on the device during low frequency
operation. This allows systems to reduce the noise associated
with the I/O’s switching.
Table 4. Extended Mode Register Definition
EM13- EM12- EM11- EM10- EM9-
BA1 BA0 A11 A10
A9
EM8-
A8
EM7-
A7
EM6- EM5-
A6 A5
EM4-
A4
10
All must be set to ‘0’
Bank
Up/Down
Driver Strength
0
EM3-
A3
0
EM2-
A2
EM1-
A1
PASR
EM0-
A0
Rev1.3, Nov. 2005
11 Page | ||
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