|
|
PDF AT697E Data sheet ( Hoja de datos )
| Número de pieza | AT697E | |
| Descripción | Rad-Hard 32 bit SPARC V8 Processor | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AT697E (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
Features
• SPARwCwwV.8DaHtaigShhePeet4rUfo.crommance Low-power 32-bit Architecture
– LEON2-FT 1.0.13 compliant
– 8 Register Windows
• Advanced Architecture:
– On-chip Amba Bus
– 5 Stage Pipeline
– 16 kbyte Multi-sets Data Cache
– 32 kbyte Multi-sets Instruction Cache
• On-chip Peripherals:
– Memory Interface
PROM Controller
SRAM Controller
SDRAM Controller
– Timers
Two 24-bit Timers
Watchdog Timer
– Two 8-bit UARTs
– Interrupt Controller with 4 External Programmable Inputs
– 32 Parallel I/O Interface
– 33MHz PCI Interface Compliant with 2.2 PCI Specification
• Integrated 32/64-bit IEEE 754 Floating-point Unit
• Fault Tolerance by Design
– Full Triple Modular Redundancy (TMR)
– EDAC Protection
– Parity Protection
• Debug and Test Facilities
– Debug Support Unit (DSU) for Trace and Debug
– IEEE 1149.1 JTAG Interface
– Four Hardware Watchpoints
• Speed Optimized Code RAM Interface
8, 16 and 40-bit boot-PROM (Flash) Interface Possibilities
• Clock: 0MHz up to 100MHz
• Core consumption: 1W
• Performance: 100 MIPS
• Operating range
– Voltages
3.3V +/- 0.30V for I/O
1.8V +/- 0.15V for Core
– Temperature
-55°C to 125°C
• Radiation Performance
– Total dose radiation capability (parametric & functional): 100Krads (Si) (target)
– SEU event rate better than 1 E-5 error/device/day (target)
– Latch up immunity better than 70 MeV.cm²/mg
• Package MCGA 349
• Mass: 9g
Rad-Hard 32 bit
SPARC V8
Processor
AT697E
Advance
Information
Summary
Rev. 4226BS–AERO–01/05
Note: This is a summary document. Contact
ATMEL for a complete document.
1
1 page  
AT697E
Pin Description
www.DataSheet4U.com
IU and FPU Signals
Memory Interface Signals
General management
PROM
SRAM
I/O
A[27:0] - Address bus (output)
A[27:0] bus carries the addresses during accesses on the memory. When no access is
performed to external memory, the address of the last access is driven.
D[31:0] - Data bus (bi-directional)
D[31:0] bus carries the data during transfers on the memory. The processor only drives
the bus during write cycles. During accesses to 8-bit areas, only D[31:24] are used.
CB[7:0] - Check bits (bi-directional)
CB[6:0] bus carries the EDAC checkbits during memory accesses. CB[7](1) takes the
value of tcb[7] in the error control register. Processor only drives CB[7:0] during write
cycles to areas programmed to be EDAC protected.
Note: 1. CB[7] is implemented to enable programming of flash memories. When only 7 bits
are useful for EDAC protection, 8 are needed for programming.
OE* - Output enable (output)
This active low output is asserted during read cycles on the memory bus
BRDY* - Bus ready (input)
This active low input indicates that the access to a memory mapped I/O area can be ter-
minated on the next rising clock edge.
READ - Read cycle (output)
This active high output is asserted during read cycles on the memory bus.
WRITE* - Write enable (output)
This active low output provides a write strobe during write cycles on the memory bus.
ROMS*[1:0] - PROM chip-select (output)
These active low outputs provide the chip-select signal for the PROM area. ROMSN[0]
is asserted when the lower half of the PROM area is accessed (0 - 0x10000000), while
ROMSN[1] is asserted for the upper half.
RAMOE*[4:0] - RAM output enable (output)
These active low signals provide an individual output enable for each RAM bank.
RAMS*[4:0] - RAM chip-select (output)
These active low outputs provide the chip-select signals for each RAM bank.
RWEN [3:0] - RAM write enable (output)
These active low outputs provide individual write strobes for each byte. RWEN[0] con-
trols D[31:24], RWEN[1] controls D[23:16], etc.
IOS* - I/O select (output)
This active low output is the chip-select signal for the memory mapped I/O area.
4226BS–AERO–01/05
5
5 Page 
AT697E
TRAPs
www.DataSheet4U.com
Timers
General Purpose Timers
Watchdog Timer
Communication
Interfaces
Serial Interfaces – UARTs
Parallel Interface
PCI interface
The AT697E supports two types of traps:
• Synchronous traps
• Asynchronous traps also called interrupts
Synchronous traps are caused by hardware responding to a particular instruction: they
occur during the instruction that caused them. Asynchronous traps occur when an exter-
nal event interrupts the processor. They are not related to any particular instruction and
occur between the execution of instructions.
Two 24-bit timers are provided on-chip. The timers can work in periodic or one-shot
mode. Both timers are clocked by a common 10-bit prescaler.
A 24-bit watchdog is provided on-chip. The watchdog is clocked by the timer prescaler.
When the watchdog reaches zero, an output signal (WDOG) is asserted. This signal can
be used to generate system reset.
Two full duplex asynchronous receiver transmitters (UART) are included. The data for-
mat of the UART’s is eight data bits with one stop bit. It is possible to choose between
no parity, even and odd parity. UART’s provide double buffering, i.e. each UART con-
sists of a transmitter holding register, a receiver holding register, a transmitter shift
register, and a receiver shift register. Each of these registers are 8-bit wide. For each
UART a data register is provided. The baud rate of both the UART’s is individually
programmable.
A 32-bit parallel I/O port is provided. 16 bits are always available and can be individually
programmed by software to be an input or an output. The additional 16 bits are only
available when the memory bus is configured for 8- or 16-bit operation.
Some of the bits have alternate usage, such as UART inputs/outputs and external inter-
rupts inputs.
The PCI implementation standing on the AT697E is PCI 2.2 compliant. It is a high per-
formance 32-bit bus with multiplexed address and data lines. It is intended for use as an
interconnect mechanism between processor/memory systems and peripheral controller
components.
4226BS–AERO–01/05
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AT697E.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AT697E | Rad-Hard 32 bit SPARC V8 Processor | ATMEL Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |