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PDF LPC2925 Data sheet ( Hoja de datos )
| Número de pieza | LPC2925 | |
| Descripción | (LPC2921 - LPC2925) ARM9 microcontroller | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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LPC2921/2923/2925
ARM9 microcontroller with CAN, LIN, and USB device
Rev. 00.01 — 24 October 2008
Preliminary data sheet
1. General description
The LPC2921/2923/2925 combine an ARM968E-S CPU core with two integrated TCM
blocks operating at frequencies of up to 125 MHz, Full-speed USB 2.0 device controller,
CAN and LIN, up to 40 kB SRAM, up to 512 kB flash memory, two 10-bit ADCs, and
multiple serial and parallel interfaces in a single chip targeted at consumer, industrial,
medical, communication, and automotive markets. To optimize system power
consumption, the LPC2921/2923/2925 has a very flexible Clock Generation Unit (CGU)
that provides dynamic clock gating and scaling.
2. Features
ARM968E-S processor running at frequencies of up to 125 MHz maximum.
Multilayer AHB system bus at 125 MHz with four separate layers.
On-chip memory:
Two Tightly Coupled Memories (TCM), 16 kB Instruction (ITCM) and 16 kB Data
TCM (DTCM).
On the LPC2925, two separate internal Static RAM (SRAM) instances, 16 kB each.
On the LPC2923 and LPC2921, one 16 kB SRAM block.
8 kB ETB SRAM, also usable for code execution and data.
Up to 512 kB high-speed flash-program memory.
16 kB true EEPROM, byte-erasable/programmable.
Dual-master, eight-channel GPDMA controller on the AHB multilayer matrix which can
be used with both I2C interfaces, the SPI interfaces, and the UARTs, as well as for
memory-to-memory transfers including the TCM memories.
Serial interfaces:
USB 2.0 full-speed device controller with dedicated DMA controller and on-chip
device PHY.
Two-channel CAN controller supporting Full-CAN and extensive message filtering.
Two LIN master controllers with full hardware support for LIN communication. The
LIN interface can be configured as UART to provide two additional UART
interfaces.
Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, and RS485
(9-bit) support.
Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep;
Tx FIFO and Rx FIFO.
Two I2C-bus interfaces.
1 page  
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5. Pinning information
5.1 Pinning
LPC2921/2923/2925
ARM9 microcontroller with CAN and LIN
1 75
LPC2921FBD100
LPC2923FBD100
LPC2925FBD100
25 51
Fig 2. Pin configuration for SOT407-1 (LQFP100)
002aae242
5.2 Pin description
5.2.1 General description
The LPC2921/2923/2925 uses three ports: port 1 with 32 pins, port 1 with 28 pins, and
port 5 with 2 pins. Ports 4/3/2 are not used. The pin to which each function is assigned is
controlled by the SFSP registers in the SCU. The functions combined on each port pin are
shown in the pin description tables in this section.
5.2.2 LQFP100 pin assignment
Table 3. LQFP100 pin assignment
Pin name
Pin Description
Function 0 (default) Function 1
TDO
1[1] IEEE 1149.1 test data out
P0[24]/TXD1/
2[1] GPIO 0, pin 24
TXDC1/SCS2[0]
UART1 TXD
P0[25]/RXD1/
RXDC1/SDO2
3[1] GPIO 0, pin 25
UART1 RXD
P0[26]/TXD1/SDI2 4[1]
GPIO 0, pin 26
-
P0[27]/RXD1/SCK2 5[1]
GPIO 0, pin 27
-
P0[28]/CAP0[0]/ 6[1] GPIO 0, pin 28
MAT0[0]
-
P0[29]/CAP0[1]/ 7[1] GPIO 0, pin 29
MAT0[1]
-
VDD(IO)
P0[30]/CAP0[2]/
MAT0[2]
8
9[1]
3.3 V power supply for I/O
GPIO 0, pin 30
-
P0[31]/CAP0[3]/
MAT0[3]
10[1]
GPIO 0, pin 31
-
VSS(IO)
11 ground for I/O
LPC2921_2923_2925_0
Preliminary data sheet
Rev. 00.01 — 24 October 2008
Function 2
CAN1 TXD
CAN1 RXD
UART1 TXD
UART1 RXD
TIMER0 CAP0
TIMER0 CAP1
TIMER0 CAP2
TIMER0 CAP3
Function 3
SPI2 SCS0
SPI2 SDO
SPI2 SDI
SPI2 SCK
TIMER0 MAT0
TIMER0 MAT1
TIMER0 MAT2
TIMER0 MAT3
© NXP B.V. 2008. All rights reserved.
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6.5 Memory map
0xFFFF FFFF
0xFFFF F000
0xFFFF C000
0xFFFF B000
0xFFFF A000
0xFFFF 9000
0xFFFF 8000
VIC
reserved
CGU1
PMU
RGU
CGU0
0xE00E 0000
0xE00C A000
0xE00C 9000
0xE00C 8000
0xE00C 7000
0xE00C 6000
0xE00C 5000
0xE00C 4000
0xE00C 3000
0xE00C 2000
0xE00C 1000
0xE00C 0000
reserved
quadrature encoder
PWM3
PWM2
PWM1
PWM0
ADC2
ADC1
reserved
MSCSS timer1
MSCSS timer0
0x2020 4000
0x2020 0000
0x2008 0000
0x2004 0000
0x2002 0000
0x2000 0000
flash controller
reserved
512 kB on-chip flash
256 kB on-chip flash
128 kB on-chip flash
0x2000 0000
0x0080 0000
0x0040 4000
0x0040 0000
no physical memory
reserved
16 kB DTCM
0x0000 4000
reserved
0x0000 0000
16 kB ITCM
PCR/VIC
subsystem
4 GB
peripherals #6
MSCSS
subsystem
remappable to
shadow area
flash
memory
2 GB
LPC2921/2923/2925
PCR/VIC control
reserved
DMA interface to TCM
reserved
ETB control
8 kB ETB SRAM
DMA controller
USB controller
reserved
peripheral subsystem #6
reserved
peripheral subsystem #4
reserved
peripheral subsystem #2
reserved
peripheral subsystem #0
reserved
16 kB AHB SRAM (LPC2925 only)
reserved
16 kB AHB SRAM
0xFFFF FFFF
0xFFFF 8000
0xF080 0000
0xF000 0000
0xE018 3000
0xE018 2000
0xE018 0000
0xE014 0000
0xE010 0000
0xE00E 0000
0xE00C 0000
0xE00A 0000
0xE008 0000
0xE006 0000
0xE004 0000
0xE002 0000
0xE000 0000
0x8000 C000
0x8000 8000
0x8000 4000
0x8000 0000
reserved
ITCM/DTCM
memory
1 GB
0 GB
reserved
on-chip flash
512 MB shadow area
ITCM/DTCM
0x4000 0000
0x2020 4000
0x2000 0000
0x0000 0000
Fig 3. LPC2921/2923/2925 memory map
peripherals #4
networking
subsystem
peripherals #2
peripheral
subsystem
peripherals #0
general
subsystem
reserved
LIN1
LIN0
CAN common regs
CAN AF regs
CAN ID LUT
reserved
I2C1
I2C0
CAN1
CAN0
0xE00A 0000
0xE008 B000
0xE008 A000
0xE008 9000
0xE008 8000
0xE008 7000
0xE008 6000
0xE008 4000
0xE008 3000
0xE008 2000
0xE008 1000
0xE008 0000
reserved
GPIO5
reserved
GPIO1
GPIO0
SPI2
SPI1
SPI0
UART1
UART0
TIMER3
TIMER2
TIMER1
TIMER0
WDT
reserved
event router
SCU
CFID
0xE006 0000
0xE005 0000
0xE004 F000
0xE004 C000
0xE004 B000
0xE004 A000
0xE004 9000
0xE004 8000
0xE004 7000
0xE004 6000
0xE004 5000
0xE004 4000
0xE004 3000
0xE004 2000
0xE004 1000
0xE004 0000
0xE002 0000
0xE000 2000
0xE000 2000
0xE000 1000
0xE000 0000
002aae232
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LPC2925.PDF ] | |
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