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PDF MCP4725 Data sheet ( Hoja de datos )
| Número de pieza | MCP4725 | |
| Descripción | 12-Bit Digital-to-Analog Converter | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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MCP4725
12-Bit Digital-to-Analog Converter with EEPROM Memory
in SOT-23-6
Features
• 12-Bit Resolution
• On-Board Non-Volatile Memory (EEPROM)
• ±0.2 LSB DNL (typical)
• External A0 Address Pin
• Normal or Power-Down Mode
• Fast Settling Time of 6 µs (typical)
• External Voltage Reference (VDD)
• Rail-to-Rail Output
• Low Power Consumption
• Single-Supply Operation: 2.7V to 5.5V
• I2CTM Interface:
- Eight Available Addresses
- Standard (100 kbps), Fast (400 kbps), and
High-Speed (3.4 Mbps) Modes
• Small 6-lead SOT-23 Package
• Extended Temperature Range: -40°C to +125°C
Applications
• Set Point or Offset Trimming
• Sensor Calibration
• Closed-Loop Servo Control
• Low Power Portable Instrumentation
• PC Peripherals
• Data Acquisition Systems
Block Diagram
A0 SCL SDA
VDD
Power-on
Reset
I2C Interface Logic
Charge
Pump
Input
Register
EEPROM
DAC Register
Resistive
String DAC
Op
VSS Amp
DESCRIPTION
The MCP4725 is a low-power, high accuracy, single
channel, 12-bit buffered voltage output Digital-to-Ana-
log Convertor (DAC) with non-volatile memory
(EEPROM). Its on-board precision output amplifier
allows it to achieve rail-to-rail analog output swing.
The DAC input and configuration data can be
programmed to the non-volatile memory (EEPROM) by
the user using I2C interface command. The non-volatile
memory feature enables the DAC device to hold the
DAC input code during power-off time, and the DAC
output is available immediately after power-up. This
feature is very useful when the DAC device is used as
a supporting device for other devices in the network.
The device includes a Power-On-Reset (POR) circuit to
ensure reliable power-up and an on-board charge
pump for the EEPROM programming voltage. The
DAC reference is driven from VDD directly. In
power-down mode, the output amplifier can be config-
ured to present a low, medium, or high resistance out-
put load.
The MCP4725 has an external A0 address pin. This A0
pin can be tied to VDD or VSS of the user’s application
board.
The MCP4725 has a two-wire I2C™ compatible serial
interface for standard (100 kHz), fast (400 kHz), or high
speed (3.4 MHz) mode.
The MCP4725 is an ideal DAC device where design
simplicity and small footprint is desired, and for applica-
tions requiring the DAC device settings to be saved
during power-off time.
The device is available in a small 6-pin SOT-23
package.
Package Type
SOT-23-6
VOUT
VSS
VDD
1
2
3
6 A0
5 SCL
4 SDA
VOUT
© 2007 Microchip Technology Inc.
DS22039C-page 1
1 page  
MCP4725
2.0 TYPICAL PERFORMANCE CURVES
www.DataSheet4U.com
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +5.0V, VSS = 0V, RL = 5 kΩ to VSS, CL = 100 pF.
0.16
0.12
0.08
0.04
0
-0.04
0
FIGURE 2-1:
1024
2048
Code
3072
4096
DNL vs. Code (VDD = 5.5V).
0.4
VDD = 2.7V
0.3
0.2
0.1
0.0
-0.1
0
1024
2048
Code
3072
4096
FIGURE 2-4:
DNL vs. Code and
Temperature (TA = -40°C to +125°C).
0.3
VDD = 5.5V
0.2
0.1
0
-0.1
0
1024
2048
Code
3072
FIGURE 2-2:
DNL vs. Code and
Temperature (TA = -40°C to +125°C).
4096
2
1
0
-1
-2 2.7V
-3
-4
0
1024
5.5V
2048
Code
3072
FIGURE 2-5:
INL vs. Code.
4096
0.3
0.2
0.1
0.0
-0.1
0
1024
2048
Code
3072
4096
FIGURE 2-3:
DNL vs. Code (VDD = 2.7V).
2
1 +25C
- 40C
0
-1
-2
-3 +85C +125C
-4
0
1024
2048
Code
3072
FIGURE 2-6:
INL vs. Code and
Temperature (VDD = 5.5V).
4096
© 2007 Microchip Technology Inc.
DS22039C-page 5
5 Page 
4.0 TERMINOLOGY
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4.1 Resolution
The resolution is the number of DAC output states that
divide the full-scale range. For the 12-bit DAC, the
resolution is 212 or the DAC code ranges from 0 to
4095.
4.2 LSB
The least significant bit or the ideal voltage difference
between two successive codes.
EQUATION 4-1:
LSBIdeal
=
V----R----E---F- =
2n
-(--V----F---u---l-l---–---S---c--a---l--e---–-----V----Z---e--r--o----–---S---c--a---l--e--)-
2n – 1
Where:
VREF = The reference voltage = VDD in the
MCP4725. This VREF is the ideal
full-scale voltage range
n = The number of digital input bits.
(n = 12 for MCP4725)
4.3 Integral Nonlinearity (INL) or
Relative Accuracy
INL error is the maximum deviation between an actual
code transition point and its corresponding ideal
transition point (straight line). Figure 2-5 shows the INL
curve of the MCP4725. The end-point method is used
for the calculation. The INL error at a given input DAC
code is calculated as:
EQUATION 4-2:
Where:
INL = (---V----O----U---T----–-----V----I--d--e---a---l-)-
LSB
VIdeal = Code*LSB
VOUT = The output voltage measured at
the given input code
MCP4725
7
INL = < -1 LSB
6
INL = - 1 LSB
5
Analog 4
Output
(LSB) 3
INL = 0.5 LSB
2
1
0
000 001 010 011 100 101 110 111
DAC Input Code
Ideal Transfer Function
Actual Transfer Function
FIGURE 4-1:
INL Accuracy.
4.4 Differential Nonlinearity (DNL)
Differential nonlinearity error (Figure 4-2) is the
measure of step size between codes in actual transfer
function. The ideal step size between codes is 1 LSB.
A DNL error of zero would imply that every code is
exactly 1 LSB wide. If the DNL error is less than 1 LSB,
the DAC guarantees monotonic output and no missing
codes. The DNL error between any two adjacent codes
is calculated as follows:
EQUATION 4-3:
Where:
ΔVOUT
DNL = Δ-----V---O----U----T----–----L----S----B--
LSB
= The measured DAC output
voltage difference between two
adjacent input codes.
© 2007 Microchip Technology Inc.
DS22039C-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MCP4725.PDF ] | |
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