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PDF EVB71122 Data sheet ( Hoja de datos )
| Número de pieza | EVB71122 | |
| Descripción | 300 to 930MHz Receiver Evaluation Board Description | |
| Fabricantes | Melexis Microelectronic Systems | |
| Logotipo |  |
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EVB71122
300 to 930MHz Receiver
Evaluation Board Description
Features
! Programmable PLL synthesizer
! 8-channel preconfigured or fully programmable SPI mode
! Double super-heterodyne receiver architecture with 2nd mixer as image rejection mixer
! Reception of FSK, FM and ASK modulated signals
! Low shut-down and operating currents
! Build-in acceptance of input frequency variations
! On-chip IF filter
www.DataSheet!!4U.cFRomuSllSyI
integrated FSK/FM
for level indication
demodulator
and ASK detection
! 2nd order low-pass data filter
! Positive and negative peak detectors
! Data slicer (with averaging or peak-detector adaptive threshold)
! EVB programming software is available on Melexis web site
Ordering Information
Part No. (see paragraph 6)
EVB71122C-315-C
EVB71122C-433-C
EVB71122C-868-C
EVB71122C-915-C
RYNote: SPI mode is default population, ABC mode according to paragraph 4.2
IMINAApplication Examples
L! General digital and analog RF receivers
Eat 300 to 930MHz
R! Tire pressure monitoring systems (TPMS)
P! Remote keyless entry (RKE)
Evaluation Board Example
! Low power telemetry systems
! Alarm and security systems
! Active RFID tags
! Remote controls
! Garage door openers
! Home and building automation
General Description
The MLX71122 is a multi-channel RF receiver IC based on a double-conversion super-heterodyne architec-
ture. It is designed to receive FSK and ASK modulated RF signals either in 8 predefined frequency channels
or frequency programmable via a 3-wire serial programming interface (SPI).
The IC is designed for a variety of applications, for example in the European bands at 433MHz and 868MHz
or for the use in North America or Asia, e.g. at 315MHz, 447MHz or 915MHz.
39012 71122 01
Rev. 001
Page 1 of 32
EVB Description
Sept/06
1 page  
1.3 Block Diagram
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
123456
LNAI LNA
www.DataSheet4U.com 31
MIX1 IF1 MIX2 IF2 IFF
LO1 LO2
LO2DIV
VCO
N/A
counter
LF
PFD
R
counter
CP RO
11 14 TNK1 12 13 TNK2 15 23
24
8
IFA
Control
Logic
9
ASK
FSK
SW1
FSK
DEMOD
SLCSEL
BIAS
28
200k
SW2
29
200k
OA1
DFO
27
PKDET+ 25
PDP
PKDET_ PDN
26
OA2
DTAO
22
SLC
32
7 17 18 19
10 16
20 21 30
Fig. 1: MLX71122 block diagram
RYThe MLX71122 receiver IC consists of the following building blocks:
INA• PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO1 and LO2,
parts of the PLL SYNTH are the voltage-controlled oscillator (VCO), the feedback dividers N/A and R,
the phase-frequency detector (PFD), the charge pump (CP) and the crystal-based reference oscillator
IM(RO)
L• Low-noise amplifier (LNA) for high-sensitivity RF signal reception
• First mixer (MIX1) for down-conversion of the RF signal to the first IF (intermediate frequency)
E• Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF
R• IF Filter (IFF) with a 2MHz center frequency and a 230kHz 3dB bandwidth
P• IF amplifier (IFA) to provide a large amount of voltage gain and an RSSI signal output
• FSK demodulator (FSK DEMOD)
• Operational amplifiers OA1 and OA2 for low-pass filtering and data slicing, respectively
• Positive (PKDET+) and negative (PKDET-) peak detectors
• Switches SW1 to select between FSK and ASK as well as SW2 to chose between averaging or peak
detector data slicer
• Control logic with 3-wire bus serial programming interface (SPI)
• Biasing circuit with modes control
For more detailed information, please refer to the latest MLX71122 data sheet revision.
39012 71122 01
Rev. 001
Page 5 of 32
EVB Description
Sept/06
5 Page 
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
2.2.5 PLL Counter Ranges
In order to cover the frequency range of about 300 to 930MHz the following counter values are implemented
in the receiver:
PLL Counter Ranges
A
0 to 31 (5bit)
N
3 to 2047 (11bit)
R
3 to 2047 (11bit)
P
32
www.DataSheetT4Uh.ecroemfore the minimum and maximum divider ratios of the PLL feedback divider are given by:
N totmin = 32 ⋅ 32 = 1024 N totmax = 2047 ⋅ 32 + 31 = 65535
2.3 SPI Description
2.3.1 General
Serial programming interface (SPI) mode can be activated by choosing SPISEL = 1 (e.g. at positive supply
voltage VCC). In this mode, the input pins 17, 18 and 19 are used as a 3-wire unidirectional serial bus inter-
face (SDEN, SDTA, SCLK). The internal latches contain all user programmable variables including counter
settings, mode bits etc.
YIn addition the MFO pin can be programmed as an output (see section 4.1.4) in order to read data from the
internal latches and it can be used as an output for different test modes as well.
ARAt each rising edge of the SCLK signal, the logic value at the SDTA terminal is written into a shift register.
The programming information is taken over into internal latches with the rising edge of SDEN. Additional
INleading bits are ignored, only the last bits are serially clocked into the shift register. A normal write operation
shifts 16 bits into the SPI, a normal read operation shifts 4 bits into the SPI and reads additional 12 bits from
IMthe MFO pin. If less than 12 data bits are shifted into SDTA during the write operation then the control regis-
ter may contain invalid information.
ELIn general a control word has the following format. Bit 0 is the Read/Write bit that determines whether it is a
read (R/W = 1) or a write (R/W = 0) sequence. The R/W bit is preceding the latch address and the
PRcorresponding data bits.
Control Word Format
MSB
LSB MSB
LSB Bit 0
Data
Latch Address Mode
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A2 A2 A0 R/W
There are two control word formats for read and for write operation. Data bits are only needed in write mode.
Read operations require only a latch address and a R/W bit.
Due to the static CMOS design, the serial interface consumes virtually no current. The SPI is a fully separate
building block and can therefore be programmed in every operational mode.
39012 71122 01
Rev. 001
Page 11 of 32
EVB Description
Sept/06
11 Page | ||
| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet EVB71122.PDF ] | |
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