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PDF SH7618 Data sheet ( Hoja de datos )
| Número de pieza | SH7618 | |
| Descripción | 32-Bit RISC Microcomputer | |
| Fabricantes | Renesas Technology | |
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REJ09B0131-0600
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
32
www.DataSheet4U.com
SH7618 Group
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperHTM RISC engine Family / SH7618 Series
SH7618
SH7618A
HD6417618
HD6417618A
Rev.6.00
Revision Date: Jun. 12, 2007
1 page  
General Precautions on Handling of Product
1. Treatment of NC Pins
Note:
Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note:
Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
www.Dat3a.ShPereot4cUes.csoinmg before Initialization
Note: When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.
Rev. 6.00 Jun. 12, 2007 Page v of xxxii
5 Page 
3.3.3 Write Access ........................................................................................................... 56
3.3.4 Write-Back Buffer .................................................................................................. 57
3.3.5 Coherency of Cache and External Memory ............................................................ 57
3.4 Memory-Mapped Cache ...................................................................................................... 58
3.4.1 Address Array ......................................................................................................... 58
3.4.2 Data Array .............................................................................................................. 59
3.4.3 Usage Examples...................................................................................................... 61
Section 4 U Memory..............................................................................................63
4.1 Features................................................................................................................................ 63
4.2 Usage Notes ......................................................................................................................... 63
Section 5 Exception Handling ...............................................................................65
5.1 Overview.............................................................................................................................. 65
www.DataSheet54U.1..c1om Types of Exception Handling and Priority.............................................................. 65
5.1.2 Exception Handling Operations .............................................................................. 66
5.1.3 Exception Handling Vector Table........................................................................... 67
5.2 Resets ................................................................................................................................... 69
5.2.1 Types of Resets....................................................................................................... 69
5.2.2 Power-On Reset ...................................................................................................... 69
5.2.3 H-UDI Reset ........................................................................................................... 70
5.3 Address Errors ..................................................................................................................... 71
5.3.1 Address Error Sources ............................................................................................ 71
5.3.2 Address Error Exception Source............................................................................. 71
5.4 Interrupts.............................................................................................................................. 72
5.4.1 Interrupt Sources..................................................................................................... 72
5.4.2 Interrupt Priority ..................................................................................................... 73
5.4.3 Interrupt Exception Handling ................................................................................. 73
5.5 Exceptions Triggered by Instructions .................................................................................. 74
5.5.1 Types of Exceptions Triggered by Instructions ...................................................... 74
5.5.2 Trap Instructions ..................................................................................................... 74
5.5.3 Illegal Slot Instructions ........................................................................................... 75
5.5.4 General Illegal Instructions..................................................................................... 75
5.6 Cases when Exceptions are Accepted .................................................................................. 76
5.7 Stack States after Exception Handling Ends ........................................................................ 77
5.8 Usage Notes ......................................................................................................................... 79
5.8.1 Value of Stack Pointer (SP) .................................................................................... 79
5.8.2 Value of Vector Base Register (VBR) .................................................................... 79
5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling .......... 79
5.8.4 Notes on Slot Illegal Instruction Exception Handling ............................................ 79
Rev. 6.00 Jun. 12, 2007 Page xi of xxxii
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SH7618.PDF ] | |
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