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PDF RT9644A Data sheet ( Hoja de datos )
| Número de pieza | RT9644A | |
| Descripción | ACPI Regulator/Controller | |
| Fabricantes | Richtek Technology Corporation | |
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Preliminary
RT9644/A
ACPI Regulator/Controller for Dual Channel
DDR Memory Systems
General Description
The RT9644/A is a complete ACPI compliant power
solution for DDR and DDR2 memory system with up to 4
DIMMs dual channel systems. This RT9644 includes one
synchronous buck controller for DDR/DDR2 VDDQ, one
DDR/DDR2 bus terminator VTT (equal to VDDQ/2) regulator
www.DataShweeitt4hUs.cooumrce and sinking ability, three LDO controllers for
VGMCH (cascode), and GMCH/CPU terminat ion
VTT_GMCH/CPU. The RT9644A includes one synchronous
buck controller for DDR/DDR2 VDDQ, one PWM controller
for VGMCH (with external MOSFET driver), one DDR/DDR2
bus terminator VTT (equal to VDDQ/2) regulator with source
and sinking ability, and two LDO controllers for
VTT_GMCH/CPU and VDAC.
These parts also provide a reference buffer for DDR/DDR2
input reference voltage generator. When during S0 state,
the VIDPGD indicates the GMCH_CPU VTT within spec
and operational. The synchronous buck DC-DC PWM is
implemented by two N-MOSFETs as upper and lower
MOSFETs with voltage mode control. The linear controllers
are implemented with one N-MOSFET with suitable
capacitance. Each output is monitored by under voltage
protection (RT9644 except VGMCHH and RT9644A except
VDAC). VDDQ PW M controller and DDR/DDR2 bus
terminator regulator have over voltage protection. Moreover,
the VDDQ PWM controller has the over current protection
by external resister adjustment. Thermal shut down is
integrated. All the internal voltage reference is fixed at
0.8V, and users can adjust the resistance divider for desired
voltage output.
Applications
l Motherboard, Desktop Servers : Single/Dual channel
DDR/DDR2 ACPI compliant
l Graphic Card : GPU and memory supply
l IA Equipments
l Telecomm Equipments
l DSP, ASIC or embedded processor and IO supplies
l High Power DC-DC Regulators
Features
l RT9644 Includes Three LDO Controllers, One LDO
Regulator and One PWM Controller
}One DDR/DDR2 VDDQ with Synchronous Buck PWM
}One DDR/DDR2 Bus Terminator VTT Regulator
Source/Sink 3A
}Two Cascode LDO Controllers for GMCH Core
}One LDO Controller for GMCH/CPU Bus Terminator
VTT_GMCH/CPU
l RT9644A Includes Two LDO Controllers, One LDO
Regulator and Two PWM Controllers
}One DDR/DDR2 VDDQ with Synchronous Buck PWM
}One VGMCH with External Richtek MOSFET Driver
}One DDR/DDR2 Bus Terminator VTT Regulator
Source/Sink 3A
}One LDO Controller for VDAC
} One LDO Controller for GMCH/CPU Bus
Terminator VTT_GMCH/CPU
l Operating with 5V and 12V Supply Voltage
l ACPI Compliant Sleep Mode Control
l Drive All Low Cost N-MOSFETs
l Voltage Mode PWM Control
}250kHz Fixed Frequency Oscillator (RT9644A: Two
PWM controllers with phase shift 90o)
}Simple Voltage Mode Loop Control
}Fast Transient Response
}Over Current Protection
l Fully Adjustable Output Voltage Down to
Compatible with DDR2
l Integrated DDR/DDR2 Reference Buffer
l Integrated VIDPGD to Indicated VTT_GMCH/CPU
Operational
l All Regulator Outputs Monitored by Under Voltage
Protection
l DDR/DDR2 VDDQ and Bus Terminator VTT Also
Integrated Over Voltage Protection
l Integrated Thermal Shut Down
l RoHS Compliant and 100% Lead (Pb)-Free
DS9644/A-01 August 2007
www.richtek.com
1
1 page  
Preliminary
RT9644/A
Pin No.
Pin Name
RT9644 RT9644A
Pin Function
14
www.DataSheet4U.com
15
16
17
A capacitor, CSS, connected between VREF_IN and ground is required. This
capacitor and the parallel combination of the Upper and Lower Divider
Impedance (RU//RL), sets the time constant for the start up ramp when
14 VREF_IN
transitioning from S3/S4/S5 to S0/S1/S2. The soft start capacitance will
determine the VTT_DDR soft start ramp by the above RC time constant.
CSS > (CVTT x VDDQ) / [10 x 2 x 1A x (RU//RL)]
FB is the error amplifier negative input that needs proper resistance divider
15 FB
connected to VDDQ. The VDDQ synchronous DC-DC buck is simple voltage
control mode. It needs a typical Type 2 compensation network from COMP to
FB (or Type 3). The reference voltage of the error amplifier is 0.8V m onitored
by under and over voltage protection.
The COMP is the output to the voltage loop error amplifier. Loop
16 COMP
compensation is achieved by connecting an AC network across COMP and
FB.
18 FB4
In RT9644, the FB4 pin connects the output of the upper V GMCH (VGMCHH)
linear regulator to this pin. The voltage at this pin is regulated via the
REFADJ4 pin (Pin 20). Generally, the FB4 is connected to VGMCHH, and
REFADJ4 = VGMCH. The VGMCHH LDO controller will set the positive input to
(VDDQ+REFADJ4)/2 as reference voltage. Then we can have the VGMCHH
equal to (VDDQ+VGMCH)/2.
In RT9644A, the FB4 is the 2nd synchronous DC-DC buck converter error
amplifier feedback. There should be the suitable AC compensation RC
network. The compensation may be Type 2 even Type 3. The feedback
voltage is monitored by the under voltage protection.
In RT9644, the FB3 pin connects the output of the lower V GMCH (VGMCH)
linear regulator to this pin through a properly sized resistor divider. The
voltage at this pin is regulated to 0.8V. This pin is monitored for under-voltage
18 20 FB3
protection.
In RT9644A, the pin connects the output of the VDAC linear regulator with
proper resister divider.
In RT9644, the DRIVE3 pin provides the gate voltage for the lower V GMCH
linear regulator pass transistor. Connect this pin to the gate terminal of an
external N-MOSFET transistor.
19 21 DRIVE3
In RT9644A, the DRIVE3 pin provides the gate voltage for the V DAC linear
regulator pass transistor. Connect this pin to the gate terminal of an external
N- MOSFET transistor.
This REFADJ4 pin controls the VGMCHH LDO controller reference voltage. To
20 -- REFADJ4 ENSURE that both upper and lower pass transistors dissipate the same
power, connecting this REFADJ4 pin to the VGMCH output rail.
The DRIVE4 pin provides the gate voltage for the upper V GMCH (VGMCHH)
21 -- DRIVE4 linear regulator. Connect this pin to the gate terminal of an external
N-MOSFET transistor.
DS9644/A-01 August 2007
To be continued
www.richtek.com
5
5 Page 
Preliminary
RT9644/A
Application Information
S5#
Overview
S3#
The RT9644/A provides complete control, drive, protection
P12V
and ACPI compliance for a regulator poweringDDR memory
VDDQ
VGMCH
systems and the GMCH core and GMCH/CPU termination VTT_GMCH/CPU
rails. It is primarily designed for computer applications
VDAC
powered from an ATX power supply.
DDR_VTT
A 250kHz Synchronous Buck Regulator with a precision
www.DataSh0e.e8t4VU.rceofmerence provides the proper Core voltage to the
system memory of the computer. An internal LDO regulator
VIDPGD
t0t1 t2t3t4t5t6
TSS
>3TSS
t7 t8t9
t10 t12 t14
t11 t13
t15
with the ability to both sink and source current and an
externally available buffered reference that tracks the
Figure 2. Timing diagram for RT9644A
VDDQ output by 50% provides the VTT termination
voltage.
S5 to S0 Transition
At the onset of a mechanical start, time t0 in Figure 1,
In RT9644, a two-stage LDO controller provides the GMCH the RT9644 receives its bias voltage from the 5V Standby
core voltage. A third LDO controller is included for the bus (5VSBY). Once the 5VSBY rail has exceeded the
regulation of the GMCH/CPU termination voltage.
POR threshold, the RT9644 will remain in an internal S5
In RT9644A, a second 250kHz PWM Buck regulator,
which requires an external MOSFET driver, provides the
GMCH core voltage. This PWM regulator is 90° out of
state until both the S3# and S5# signal have transitioned
high and the 12V POR threshold has been exceeded by
the +12V rail from the ATX, which occurs at time t1.
phase with the PWM regulator used for the Memory core. Once all of these conditions are met, the PWM error
Two additional LDO controllers are included, one for the amplifier will first be reset by internally shorting the COMP
regulation of the GMCH/CPU termination rail and the pin to the FB pin. This reset lasts for 3-4 soft-start cycles,
second for the DAC.
Then digital soft-start sequence will begin. Each regulator
ACPI State Transitions
is enabled and soft-started according to a preset
sequence.
ACPI compliance is realized through the S3# and S5#
sleep signals and through monitoring of the 12V ATX bus.
Figure 1 and Figure 2 shows how the RT9644 and RT9644A
individual regulators are controlled during all state
transitions.
At time t2 the VDDQ rail and the upper VGMCH LDO rail of
RT9644 are digitally soft-started.
The digital soft-start for the PWM regulator is
accomplished by clamping the error amplifier reference
input to a level proportional to the internal digital soft-start
S5#
S3#
P12V
VDDQ
VGMCHH
VGMCH
VTT_GMCH/CPU
voltage. As the soft-start voltage slews up, the PWM
comparator generates PHASE pulses of increasing width
that charge the output capacitor(s).
This method provides a rapid and controlled rising output
voltage. The linear regulators, with the exception of the
internal DDR_VTT LDO, are soft-started in a similar manner.
DDR_VTT
VIDPGD
TSS
t0t1 t2t3t4t5t6
>3TSS
t7 t8t9
t10 t12 t14
t11 t13
Figure 1. Timing diagram for RT9644
The error amplifier reference is clamped to the internal
digital soft-start voltage. As the soft-start voltage ramps
up, the respective DRIVE pin voltages increase, thus
t15
enhancing the N-MOSFETs and charging the output
DS9644/A-01 August 2007
www.richtek.com
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet RT9644A.PDF ] | |
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