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PDF LTC2306 Data sheet ( Hoja de datos )
| Número de pieza | LTC2306 | |
| Descripción | (LTC2302 / LTC23026) 12-Bit ADC | |
| Fabricantes | Linear Technology Corporation | |
| Logotipo |  |
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FEATURES
n 12-Bit Resolution
n 500ksps Sampling Rate
n Low Noise: SINAD = 72.8dB
n Guaranteed No Missing Codes
n Single 5V Supply
www.DataShneetA4Uu.tcoo-mShutdown Scales Supply Current with Sample
Rate
n Low Power: 14mW at 500ksps
70μW at 1ksps
35μW Sleep Mode
n 1-Channel (LTC2302) and 2-Channel (LTC2306)
Versions
n Unipolar or Bipolar Input Ranges (Software
Selectable)
n Internal Conversion Clock
n SPI/MICROWIRE™ Compatible Serial Interface
n Separate Output Supply OVDD (2.7V to 5.25V)
n Software Compatible with the LTC2308
n 10-Pin (3mm × 3mm) DFN Package
APPLICATIONS
n High Speed Data Acquisition
n Industrial Process Control
n Motor Control
n Accelerometer Measurements
n Battery-Operated Instruments
n Isolated and/or Remote Data Acquisition
LTC2302/LTC2306
Low Noise, 500ksps,
1-/2-Channel, 12-Bit ADCs
DESCRIPTION
The LTC®2302/LTC2306 are low noise, 500ksps, 1-/2-chan-
nel, 12-bit ADCs with an SPI/MICROWIRE compatible
serial interface. These ADCs include a fully differential
sample-and-hold circuit to reduce common mode noise.
The internal conversion clock allows the external serial
output data clock (SCK) to operate at any frequency up
to 40MHz.
The LTC2302/LTC2306 operate from a single 5V supply
and draw just 2.8mA at a sample rate of 500ksps. The
auto-shutdown feature reduces the supply current to 14μA
at a sample rate of 1ksps.
The LTC2302/LTC2306 are packaged in a tiny 10-pin 3mm
× 3mm DFN. The low power consumption and small size
make the LTC2302/LTC2306 ideal for battery-operated
and portable applications, while the 4-wire SPI compat-
ible serial interface makes these ADCs a good match for
isolated or remote data acquisition systems.
TYPE
Int Reference
Ext Reference
NUMBER OF INPUT CHANNELS
128
LTC2308
LTC2302
LTC2306
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
5V
10μF
0.1μF
0.1μF
2.7V TO 5.25V
VDD OVDD
ANALOG INPUTS CH0 (IN+)
0V TO 4.096V UNIPOLAR
±2.048V BIPOLAR CH1 (IN–)
ANALOG
INPUT
MUX
+ 12-BIT
–
500ksps
ADC
PIN NAMES IN PARENTHESIS
REFER TO LTC2302
GND
LTC2302
LTC2306
SERIAL
PORT
SDI
SDO SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
SCK OR SHIFT REGISTER
CONVST
0.1μF
VREF
10μF
23026 TA01
8192 Point FFT, fIN = 1kHz (LTC2306)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
0
fSMPL = 500kHz
SINAD = 72.8dB
THD = –88.7dB
50 100 150 200 250
FREQUENCY (kHz)
23026 TA01b
23026f
1
1 page  
LTC2302/LTC2306
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
fSMPL(MAX)
fSCK
tWHCONV
tHD
tSUDI
tWHCLK
www.DataShteWeLtC4LUK.com
tWLCONVST
tHCONVST
tCONV
tACQ
tdDO
thDO
ten
tdis
tr
tf
tCYC
PARAMETER
Maximum Sampling Frequency
Shift Clock Frequency
CONVST High Time
Hold Time SDI After SCK↑
Setup Time SDI Stable Before SCK↑
SCK High Time
SCK Low Time
CONVST Low Time During Data Transfer
Hold Time CONVST Low After Last SCK↓
Conversion Time
Acquisition Time
SDO Data Valid After SCK↓
SDO Hold Time SCK↓
SDO Valid After CONVST↓
Bus Relinquish Time
SDO Rise Time
SDO Fall Time
Total Cycle Time
CONDITIONS
(Note 9)
fSCK = fSCK(MAX)
fSCK = fSCK(MAX)
(Note 9)
(Note 9)
7th SCK↑ to CONVST↑ (Note 9)
CL = 25pF (Note 9)
CL = 25pF
CL = 25pF
CL = 25pF
CL = 25pF
CL = 25pF
MIN TYP MAX UNITS
l 500 kHz
l 40 MHz
l 20
ns
l 2.5
ns
l0
ns
l 10
ns
l 10
ns
l 410
ns
l 20
ns
l
1.3 1.6
μs
l 240
ns
l
10.8 12.5
ns
l4
ns
l
11 15
ns
l
11 15
ns
4 ns
4 ns
2 μs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with VDD and OVDD
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above VDD,
they will be clamped by internal diodes. These products can handle input
currents greater than 100mA below ground or above VDD without latchup.
Note 4: VDD = 5V, OVDD = 5V, VREF = 4.096V, fSMPL = 500ksps, unless
otherwise specified.
Note 5: Linearity, offset and full-scale specifications apply for a single-
ended analog input with respect to GND for the LTC2306 and IN+ with
respect to IN– tied to GND for the LTC2302.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 and 1111 1111
1111. Unipolar zero error is the offset voltage measured from +0.5LSB
when the output code flickers between 0000 0000 0000 and 0000 0000
0001.
Note 8: Full-scale bipolar error is the worst-case of –FS or +FS untrimmed
deviation from ideal first and last code transitions and includes the effect
of offset error. Unipolar full-scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
Note 9: Guaranteed by design, not subject to test.
Note 10: All specifications in dB are referred to a full-scale ±2.048V input
with a 4.096V reference voltage.
Note 11: Full linear bandwidth is defined as the full-scale input frequency
at which the SINAD degrades to 60dB or 10 bits of accuracy.
23026f
5
5 Page 
LTC2302/LTC2306
BLOCK DIAGRAM
www.DataSheet4U.com
CH0 (IN+)
CH1 (IN–)
VDD OVDD
ANALOG
INPUT
MUX
+ 12-BIT
–
500ksps
ADC
PIN NAMES IN PARENTHESIS
REFER TO LTC2302
GND
LTC2302
LTC2306
SERIAL
PORT
SDI
SDO
SCK
CONVST
VREF
23026 BD
TEST CIRCUITS
Load Circuit for tdis Waveform 1
SDO
VDD
3k
TEST POINT
CL
23026 TC01
Load Circuit for tdis Waveform 2, ten
SDO
TEST POINT
3k CL
23026 TC02
TIMING DIAGRAMS
Voltage Waveforms for SDO Delay Times, tdDO and thDO
SCK
VIL
tdDO
thDO
SDO
VOH
VOL
23026 TD01
Voltage Waveforms for tdis
CONVST
VIH
SDO
WAVEFORM 1
(SEE NOTE 1)
90%
tdis
SDO
WAVEFORM 2
(SEE NOTE 2)
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
23026 TD02
23026f
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC2306.PDF ] | |
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