|
|
PDF LTC2308 Data sheet ( Hoja de datos )
| Número de pieza | LTC2308 | |
| Descripción | 12-Bit ADC | |
| Fabricantes | Linear Technology Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LTC2308 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
LTC2308
Low Noise, 500ksps,
8-Channel, 12-Bit ADC
FEATURES
■ 12-Bit Resolution
■ 500ksps Sampling Rate
■ Low Noise: SINAD = 73.3dB
■ Guaranteed No Missing Codes
www.DataSh■eetS4Uin.cgolme 5V Supply
■ Auto-Shutdown Scales Supply Current with Sample
Rate
■ Low Power: 17.5mW at 500ksps
0.9mW Nap Mode
35μW Sleep Mode
■ Internal Reference
■ Internal 8-Channel Multiplexer
■ Internal Conversion Clock
■ SPI/MICROWIRETM Compatible Serial Interface
■ Unipolar or Bipolar Input Ranges (Software Selectable)
■ Separate Output Supply OVDD (2.7V to 5.25V)
■ 24-Pin 4mm × 4mm QFN Package
APPLICATIONS
■ High Speed Data Acquisition
■ Industrial Process Control
■ Motor Control
■ Accelerometer Measurements
■ Battery Operated Instruments
■ Isolated and/or Remote Data Acquisition
DESCRIPTION
The LTC®2308 is a low noise, 500ksps, 8-channel, 12-bit
ADC with an SPI/MICROWIRE compatible serial interface.
This ADC includes an internal reference and a fully differ-
ential sample-and-hold circuit to reduce common-mode
noise. The internal conversion clock allows the external
serial output data clock (SCK) to operate at any frequency
up to 40MHz.
The LTC2308 operates from a single 5V supply and draws
just 3.5mA at a sample rate of 500ksps. The auto-shutdown
feature reduces the supply current to 200μA at a sample
rate of 1ksps.
The LTC2308 is packaged in a small 24-pin 4mm × 4mm
QFN. The internal 2.5V reference and 8-channel multiplexer
further reduce PCB board space requirements.
The low power consumption and small size make the
LTC2308 ideal for battery operated and portable appli-
cations, while the 4-wire SPI compatible serial interface
makes this ADC a good match for isolated or remote data
acquisition systems.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
5V
0.1μF
10μF
10μF 0.1μF
CH0
CH1
CH2
CH0-CH7
CH3
ANALOG INPUTS CH4
0V TO 4.096V UNIPOLAR
p2.048V BIPOLAR
CH5
CH6
CH7
COM
AVDD
ANALOG
INPUT
MUX
+
–
DVDD
LTC2308
OVDD
2.7V TO 5.25 V
0.1μF
12-BIT
500ksps
ADC
SERIAL
PORT
INTERNAL
2.5V REF
SDI
SDO SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
SCK OR SHIFT REGISTER
CONVST
VREF
2.2μF
GND
0.1μF
REFCOMP
10μF
2308 TA01
8192 Point FFT, fIN = 1kHz
0
–10 fSMPL = 500kHz
–20
SINAD = 73.6dB
THD = –89.5dB
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
0
50 100 150 200 250
FREQUENCY (kHz)
2308 G03
2308f
1
1 page  
LTC2308
TIMING CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
fSMPL(MAX)
Maximum Sampling Frequency
● 500 kHz
fSCK Shift Clock Frequency
● 40 MHz
tWHCONV
CONVST High Time
(Note 9)
● 20
ns
tHD Hold Time SDI After SCK↑
● 2.5
ns
tSUDI Setup Time SDI Valid Before SCK↑
●0
ns
tWHCLK
SCK High Time
fSCK = fSCK(MAX)
● 10
ns
www.DataShteWeLtC4LUK.com SCK Low Time
fSCK = fSCK(MAX)
● 10
ns
tWLCONVST
CONVST Low Time During Data Transfer (Note 9)
● 410
ns
tHCONVST
Hold Time CONVST Low After Last SCK↓ (Note 9)
● 20
ns
tCONV
Conversion Time
● 1.3 1.6 μs
tACQ Acquisition Time
7th SCK↑ to CONVST↑ (Note 9)
● 240
ns
tREFWAKE
REFCOMP Wakeup Time (Note 12)
CREFCOMP = 10μF, CREF = 2.2μF
200 ms
tdDO SDO Data Valid After SCK↓
CL = 25pF (Note 9)
● 10.8 12.5 ns
thDO SDO Hold Time After SCK↓
CL = 25pF
●4
ns
ten SDO Valid After CONVST↓
CL = 25pF
● 11 15 ns
tdis Bus Relinquish Time
CL = 25pF
● 11 15 ns
tr SDO Rise Time
tf SDO Fall Time
tCYC Total Cycle Time
CL = 25pF
CL = 25pF
4 ns
4 ns
2 μs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with AVDD, DVDD and
OVDD wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above VDD,
they will be clamped by internal diodes. These products can handle input
currents greater than 100mA below ground or above VDD without latchup.
Note 4: AVDD = 5V, DVDD = 5V, OVDD = 5V, fSMPL = 500kHz, internal
reference unless otherwise specified.
Note 5: Linearity, offset and full-scale specifications apply for a single-
ended analog input with respect to COM.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 and 1111 1111
1111. Unipolar zero error is the offset voltage measured from +0.5LSB
when the output code flickers between 0000 0000 0000 and
0000 0000 0001.
Note 8: Full-scale bipolar error is the worst-case of –FS or +FS untrimmed
deviation from ideal first and last code transitions and includes the effect
of offset error. Unipolar full-scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
Note 9: Guaranteed by design, not subject to test.
Note 10: All specifications in dB are referred to a full-scale ±2.048V input
with a 2.5V reference voltage.
Note 11: Full linear bandwidth is defined as the full-scale input frequency
at which the SINAD degrades to 60dB or 10 bits of accuracy.
Note 12: REFCOMP wakeup time is the time required for the REFCOMP pin
to settle within 0.5LSB at 12-bit resolution of its final value after waking up
from SLEEP mode.
2308f
5
5 Page 
LTC2308
APPLICATIONS INFORMATION
Overview
The LTC2308 is a low noise, 500ksps, 8-channel, 12-bit
successive approximation register (SAR) A/D converter.
The LTC2308 includes a precision internal reference, a
configurable 8-channel analog input multiplexer (MUX)
and an SPI-compatible serial port for easy data transfers.
The ADC may be configured to accept single-ended or
differential signals and can operate in either unipolar or
www.DataShbeiept4oUla.crommode. A sleep mode option is also provided to
save power during inactive periods.
Conversions are initiated by a rising edge on the CONVST
input. Once a conversion cycle has begun, it cannot be
restarted. Between conversions, a 6-bit input word (DIN)
at the SDI input configures the MUX and programs vari-
ous modes of operation. As the DIN bits are shifted in,
data from the previous conversion is shifted out on SDO.
After the 6 bits of the DIN word have been shifted in, the
ADC begins acquiring the analog input in preparation for
the next conversion as the rest of the data is shifted out.
The acquire phase requires a minimum time of 240ns
for the sample-and-hold capacitors to acquire the analog
input signal.
During the conversion, the internal 12-bit capacitive
charge-redistribution DAC output is sequenced through a
successive approximation algorithm by the SAR starting
from the most significant bit (MSB) to the least significant
bit (LSB). The sampled input is successively compared
with binary weighted charges supplied by the capacitive
DAC using a differential comparator. At the end of a conver-
sion, the DAC output balances the analog input. The SAR
contents (a 12-bit data word) that represent the sampled
analog input are loaded into 12 output latches that allow
the data to be shifted out.
Programming the LTC2308
The various modes of operation of the LTC2308 are
programmed by a 6-bit DIN word. The SDI data bits are
loaded on the rising edge of SCK, with the S/D bit loaded
on the first rising edge and the SLP bit on the sixth rising
edge (see Figure 8 in the Timing and Control section). The
input data word is defined as follows:
S/D O/S S1 S0 UNI SLP
S/D = SINGLE-ENDED/DIFFERENTIAL BIT
O/S = ODD/SIGN BIT
S1 = ADDRESS SELECT BIT 1
S0 = ADDRESS SELECT BIT 0
UNI = UNIPOLAR/BIPOLAR BIT
SLP = SLEEP MODE BIT
2308f
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC2308.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LTC2301 | (LTC2301 / LTC2305) 12-Bit ADCs | Linear Technology Corporation |
| LTC2302 | (LTC2302 / LTC23026) 12-Bit ADC | Linear Technology Corporation |
| LTC2305 | (LTC2301 / LTC2305) 12-Bit ADCs | Linear Technology Corporation |
| LTC2306 | (LTC2302 / LTC23026) 12-Bit ADC | Linear Technology Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |