PDF ADS5240 Data sheet ( Hoja de datos )

Número de pieza	ADS5240
Descripción	40MSPS ADC
Fabricantes	Burr-Brown Corporation
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No Preview Available ! BurrĆBrown Products from Texas Instruments ¨ ADS5240 SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 4-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface FEATURES • Maximum Sample Rate: 40MSPS • 12-Bit Resolution • No Missing Codes • Power Dissipation: 607mW • CMOS Technology • Simultaneous Sample-and-Hold • 70.5dBFS SNR at 10MHz IF • Internal and External References • 3.3V Digital/Analog Supply • Serialized LVDS Outputs • Integrated Frame and Bit Patterns • MSB and LSB First Modes • Option to Double LVDS Clock Output Currents • Pin- and Format-Compatible Family • HTQFP-64 PowerPAD™ Package APPLICATIONS • Portable Ultrasound Systems • Tape Drives • Test Equipment • Optical Networking DESCRIPTION The ADS5240 is a high-performance, 4-channel, 40MSPS analog-to-digital converter (ADC). Internal references are provided, simplifying system design requirements. Low power consumption allows for the highest of system integration densities. Serial LVDS (low-voltage differential signaling) outputs reduce the number of interface lines and package size. RELATED PRODUCTS MODEL RESOLUTION (BITS) ADS5242(1) 12 (1) Available Q1 2005. SAMPLE RATE (MSPS) CHANNELS 65 4 An integrated phase lock loop multiplies the incoming ADC sampling clock by a factor of 12. This 12x clock is used in the process of serializing the data output from each channel. The 12x clock is also used to generate a 1x and a 6x clock, both of which are transmitted as LVDS clock outputs. The 6x clock is denoted by the differential pair LCLKP and LCLKN, while the 1x clock is denoted by ADCLKP and ADCLKN. The word output of each ADC channel can be transmitted either as MSB or LSB first. The bit coinciding with the rising edge of the 1x clock output is the first bit of the word. Data is to be latched by the receiver on both the rising and falling edges of the 6x clock. The ADS5240 provides internal references, or can optionally be driven with external references. Best performance can be achieved through the internal reference mode. The device is available in an HTQFP-64 PowerPAD package and is specified over a -40°C to +85°C operating range. 6X ADCLK ADCLK PLL 1X ADCLK IN 1 P IN1N S/H IN 2 P IN2N S/H IN 3 P IN3N S/H IN 4 P IN4N S/H 12− Bit ADC 12− Bit ADC 12− Bit ADC 12− Bit ADC Serializer Serializer Serializer Serializer Reference R e g is te rs C o n tr o l INT /E X T LCLKP LCLKN ADC LKP ADC LKN OUT 1P OUT 1N OUT 2P OUT 2N OUT 3P OUT 3N OUT 4P OUT 4N Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated 1 page ADS5240 www.ti.com SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 AC CHARACTERISTICS TMIN = -40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V differential, transformer coupled inputs, -1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted. PARAMETER DYNAMIC CHARACTERISTICS SFDR Spurious-Free Dynamic Range HD2 2nd-Order Harmonic Distortion HD3 3rd-Order Harmonic Distortion SNR Signal-to-Noise Ratio SINAD Signal-to-Noise and Distortion IMD Two-Tone Intermodulation Distortion ENOB Effective Number of Bits Crosstalk CONDITIONS ADS5240 MIN TYP MAX UNITS fIN = 1MHz 87 fIN = 5MHz 78 85 fIN = 10MHz 85 fIN = 1MHz 95 fIN = 5MHz 85 95 fIN = 10MHz 90 fIN = 1MHz 87 fIN = 5MHz 78 85 fIN = 10MHz 85 fIN = 1MHz 70.5 fIN = 5MHz 68 70.5 fIN = 10MHz 70 fIN = 1MHz 70 fIN = 5MHz 67 70 fIN = 10MHz 69.5 f1 = 9.5MHz at -7dBFS f2 = 10.2MHz at -7dBFS -88 fIN = 5MHz 11.3 Signal Applied to 3 Channels; Measurement Taken on the Channel with No Input Signal -90 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBFS dBFS dBFS dBFS dBFS dBFS dBc Bits dBc 5 5 Page ADS5240 www.ti.com PIN DESCRIPTIONS NAME AVDD IN1P IN1N AVSS IN2P IN2N LVSS PD LCLKP LCLKN NC OUT1P OUT1N LVDD OUT2P OUT2N OUT3P OUT3N OUT4P OUT4N ADCLKP ADCLKN RESET IN3P IN3N IN4P IN4N ISET VCM REFB REFT INT/EXT ADCLK CS SDATA SCLK PIN # 1, 5, 10, 39, 44, 48, 55, 60 2 3 4, 6, 9, 40, 43, 45, 49, 57-59, 64 7 8 11, 13, 14, 22, 28, 35, 36, 38 12 15 16 17, 18, 31, 32 19 20 21, 27 23 24 25 26 29 30 33 34 37 41 42 46 47 50 51 52 53 54 56 61 62 63 SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 I/O DESCRIPTION I Analog Power Supply I Channel 1 Differential Analog Input High I Channel 1 Differential Analog Input Low I Analog Ground I Channel 2 Differential Analog Input High I Channel 2 Differential Analog Input Low I LVDS Ground I Power-Down; 0 = Normal, 1 = Power-Down O Positive LVDS Clock O Negative LVDS Clock — No Connection O Channel 1 Positive LVDS Data Output O Channel 1 Negative LVDS Data Output I LVDS Power Supply O Channel 2 Positive LVDS Data Output O Channel 2 Negative LVDS Data Output O Channel 3 Positive LVDS Data Output O Channel 3 Negative LVDS Data Output O Channel 4 Positive LVDS Data Output O Channel 4 Negative LVDS Data Output O Positive LVDS ADC Clock Output O Negative LVDS ADC Clock Output I Reset Registers to Default; 0 = Reset, 1 = Normal I Channel 3 Differential Analog Input High I Channel 3 Differential Analog Input Low I Channel 4 Differential Analog Input High I Channel 4 Differential Analog Input Low I/O Bias Current Setting Resistor of 56.2kΩ to Ground O Common-Mode Output Voltage I/O Reference Bottom Voltage (2Ω resistor in series with 0.1µF capacitor to ground) I/O Reference Top Voltage (2Ω resistor in series with 0.1µF capacitor to ground) I Internal/External Reference Select; 0 = External, 1 = Internal I Data Converter Clock Input I Chip-Select; 0 = Select, 1 = No Select I Serial Data Input I Serial Data Clock 11 11 Page

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