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PDF AS7C33256PFD36A Data sheet ( Hoja de datos )
| Número de pieza | AS7C33256PFD36A | |
| Descripción | (AS7C33256PFD32A / AS7C33256PFD36A) 3.3V 256K x 32/36 pipelined burst synchronous SRAM | |
| Fabricantes | Alliance Semiconductor Corporation | |
| Logotipo |  |
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December 2004
AS7C33256PFD32A
AS7C33256PFD36A
®
3.3V 256K × 32/36 pipelined burst synchronous SRAM
Features
• Organization: 262,144 words x 32 or 36 bits
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.5/4.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous register-to-register operation
• Dual-cycle deselect
• Asynchronous output enable control
• Available in100-pin TQFP
• Individual byte write and global write
• Multiple chip enables for easy expansion
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
www.DataSheet4U.com
Logic block diagram
CLK
ADV
ADSC
ADSP
A[17:0]
BWE
GWE
BWd
BWc
BWb
BWa
CE0
CE1
CE2
Selection guide
ZZ
OE
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
18
Power
down
LBO
CLK
CE
Q0
Burst logic
CLR Q1
D Q 18 2 16 2 18
CCELKrAedgdisrteesrs
256K × 32/36
Memory
array
D BytDeQwdriteQ
registers
CLK
DBytDeQwcriteQ
registers
CLK
DBytDeQwbriteQ
registers
CLK
DBytDeQwariteQ
registers
CLK
36/32 36/32
4
DQ
Enable
CE register
CLK
D Enable Q
delay
register
CLK
OE
Output
registers
CLK
Input
registers
CLK
36/32
DQ[a:d]
–166
6
166
3.5
475
130
30
–133
7.5
133
4
425
100
30
Units
ns
MHz
ns
mA
mA
mA
12/1/04, v.1.2
Alliance Semiconductor
P. 1 of 20
Copyright ©Alliance Semiconductor. All rights reserved.
1 page  
AS7C33256PFD32A
AS7C33256PFD36A
®
Signal descriptions
Signal
CLK
A, A0, A1
DQ[a,b,c,d]
I/O
I
I
I/O
CE0 I
www.DataSheet4CUE.c1o,mCE2 I
ADSP
I
ADSC
ADV
GWE
I
I
I
BWE
I
BW[a,b,c,d] I
OE I
LBO
ZZ
NC
I
I
-
Properties
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
ASYNC
-
Description
Clock. All inputs except OE, ZZ, LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0
is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more
information.
Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on
clock edges when ADSC is active or when CE0 and ADSP are active.
Address strobe processor. Asserted LOW to load a new bus address or to enter standby
mode.
Address strobe controller. Asserted LOW to load a new address or to enter standby
mode.
Advance. Asserted LOW to continue burst read/write.
Global write enable. Asserted LOW to write all 32/36 bits. When HIGH, BWE and
BW[a:d] control write enable.
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d]
inputs.
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
LOW. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a
write cycle. If all BW[a:d] are inactive the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in
read mode.
Selects Burst mode. When tied to VDD or left floating, device follows Interleaved Burst
order. When driven Low, device follows linear Burst order. This signal is internally
pulled High.
Snooze. Places device in LOW power mode; data is retained. Connect to GND if unused.
No connect
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE
MODE.
12/1/04, v.1.2
Alliance Semiconductor
P. 5 of 20
5 Page 
AS7C33256PFD32A
AS7C33256PFD36A
®
Timing characteristics for 2.5 V I/O operation
Parameter
Clock frequency
Cycle time
Clock access time
Output enable low to data valid
Clock high to output low Z
www.DataSheet4DUa.ctaomoutput invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
Clock low pulse width
Address setup to clock high
Data setup to clock high
Write setup to clock high
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
ADV setup to clock high
ADSP setup to clock high
ADSC setup to clock high
ADV hold from clock high
ADSP hold from clock high
ADSC hold from clock high
1 See “Notes” on page 17
Symbol
fMax
tCYC
tCD
tOE
tLZC
tOH
tLZOE
tHZOE
tHZC
tOHOE
tCH
tCL
tAS
tDS
tWS
tCSS
tAH
tDH
tWH
tCSH
tADVS
tADSPS
tADSCS
tADVH
tADSPH
tADSCH
–166
Min Max
– 166
6–
- 3.8
– 3.5
0–
1.5 –
0–
– 3.5
– 3.5
0–
2.4 –
2.3 –
1.7 –
1.7 –
1.7 –
1.7 –
0.7 –
0.7 –
0.7 –
0.7 –
1.7 –
1.7 –
1.7 –
0.7 –
0.7 –
0.7 –
–133
Min Max
– 133
7.5 –
- 4.2
– 4.0
0–
1.5 –
0–
– 4.0
– 4.0
0–
2.5 –
2.5 –
1.7 –
1.7 –
1.7 –
1.7 –
0.7 –
0.7 –
0.7 –
0.7 –
1.7 –
1.7 –
1.7 –
0.7 –
0.7 –
0.7 –
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes1
2,3,4
2
2,3,4
2,3,4
2,3,4
5
5
6
6
6,7
6,8
6
6
6,7
6,8
6
6
6
6
6
6
Snooze Mode Electrical Characteristics
Description
Current during Snooze Mode
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
Conditions
ZZ > VIH
Symbol
ISB2
tPDS
tPUS
tZZI
tRZZI
Min
2
2
0
Max Units
30 mA
cycle
cycle
2 cycle
12/1/04, v.1.2
Alliance Semiconductor
P. 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AS7C33256PFD36A.PDF ] | |
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| AS7C33256PFD36A | (AS7C33256PFD32A / AS7C33256PFD36A) 3.3V 256K x 32/36 pipelined burst synchronous SRAM | Alliance Semiconductor Corporation |
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