PDF AS7C33256PFD18B Data sheet ( Hoja de datos )

Número de pieza	AS7C33256PFD18B
Descripción	3.3V 256K x 18 pipeline burst synchronous SRAM
Fabricantes	Alliance Semiconductor Corporation
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February 2005 AS7C33256PFD18B ® 3.3V 256K × 18 pipeline burst synchronous SRAM Features • Organization: 262,144 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous register-to-register operation • Double-cycle deselect • Asynchronous output enable control • Available in 100-pin TQFP package www.DataSheet4U.com • Individual byte write and global write • Multiple chip enables for easy expansion • Linear or interleaved burst control • Snooze mode for reduced power-standby • Common data inputs and data outputs • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ Logic block diagram CLK ADV ADSC ADSP A[17:0] GWE BWb BWE BWa CCEE01 CE2 ZZ OE 18 Power down LBO CLK CS Burst logic CLR DQ CS Aredgdisrteesrs CLK 18 16 18 256K × 18 Memory array D DQb Q BryetgeisWterriste CLK D DQa Q BryetgeisWterriste CLK D Enable Q register CE CLK D Enable Q redgeilsatyer CLK 18 18 2 OE Output registers CLK Input registers CLK 18 DQ [a,b] Selection guide Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) –200 5 200 3.0 375 130 30 –166 6 166 3.5 350 100 30 –133 7.5 133 4 325 90 30 Units ns MHz ns mA mA mA 1/31/05; v.1.2 Alliance Semiconductor P. 1 of 19 Copyright © Alliance Semiconductor. All rights reserved. 1 page AS7C33256PFD18B ® Signal descriptions Signal I/O Properties CLK I CLOCK A,A0,A1 I SYNC DQ[a,b] I/O SYNC CE0 www.DataSheet4U.com I SYNC CE1, CE2 I SYNC ADSP I SYNC ADSC ADV GWE I SYNC I SYNC I SYNC BWE I SYNC BW[a,b] I SYNC OE I ASYNC LBO I STATIC ZZ I ASYNC NC - - Description Clock. All inputs except OE, ZZ, LBO are synchronous to this clock. Address. Sampled when all chip enables are active and ADSC or ADSP are asserted. Data. Driven as output when the chip is enabled and OE is active. Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information. Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on clock edges when ADSC is active or when CE0 and ADSP are active. Address strobe (processor). Asserted LOW to load a new address or to enter standby mode. Address strobe (controller). Asserted LOW to load a new address or to enter standby mode. Burst advance. Asserted LOW to continue burst read/write. Global write enable. Asserted LOW to write all 18 bits. When HIGH, BWE and BW[a,b] control write enable. Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b] inputs. Write enables. Used to control write of individual bytes when GWE = HIGH and BWE = LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the cycle is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle. Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read mode. Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When driven Low, device follows linear Burst order. This signal is internally pulled High. Snooze. Places device in low power mode; data is retained. Connect to GND if unused. No connect Snooze Mode SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state. The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. 1/31/05; v.1.2 Alliance Semiconductor P. 5 of 19 5 Page AS7C33256PFD18B Key to switching waveforms ® Rising input Falling input don’t care Timing waveform of read cycle CLK www.DataSheet4U.com tADSPS ADSP tADSPH tCYC tCH tCL ADSC tADSCS tADSCH tAS tAH Address A1 A2 LOAD NEW ADDRESS A3 GWE, BWE tWS tWH tCSS CE0, CE2 tCSH Undefined CE1 ADV OE Dout tADVS tADVH ADV inserts wait states tOE tLZOE Q(A1) tHZOEtOH Q(A2) tCD Q(A2Ý01) Q(A2Ý10) tHZC Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Read Q(A1) Suspend Read Q(A1) Read Burst Burst Suspend Burst Read Burst Burst Burst Q(A2) Read Read Read Read Q(A3) Read Read Read DSEL* Q(A 2Ý01) Q(A 2Ý10) Q(A 2Ý10) Q(A 2Ý11) Q(A 3Ý01) Q(A 3Ý10) Q(A 3Ý11) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care. *Outputs are disabled within two clk cycles after DSEL command 1/31/05; v.1.2 Alliance Semiconductor P. 11 of 19 11 Page

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