PDF AS7C33256NTF32A Data sheet ( Hoja de datos )

Número de pieza	AS7C33256NTF32A
Descripción	(AS7C33256NTF32A / AS7C33256NTF36A) 3.3V 256K x 2/36 Flowthrough Synchronous SRAM
Fabricantes	Alliance Semiconductor Corporation
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No Preview Available ! November 2004 AS7C33256NTF32A AS7C33256NTF36A ® 3.3V 256K×32/36 Flowthrough Synchronous SRAM with NTDTM Features • Organization: 262,144 words × 32 or 36 bits • NTD™ architecture for efficient bus operation • Fast clock to data access: 7.5/8.5/10 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous operation • Flow-through mode • Asynchronous output enable control www.DataShee•t4AUv.caoimlable in 100-pin TQFP • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion Logic Block Diagram A[17:0] 18 D Q Address register Burst logic CLK CE0 CE1 CE2 R/W BWa BWb BWc BWd ADV / LD LBO ZZ Control logic CLK DQ[a,b,c,d] 32/36 D Data Input Q Register CLK • 3.3 core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • 30 mW typical standby power • Self-timed write cycles • Interleaved or linear burst modes • Snooze mode for standby operation 18 DQ Write delay addr. registers CLK 18 CLK 32/36 256K x 32/36 SRAM Array 32/36 32/36 CLK CEN Selection Guide Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 32/36 Output Buffer OE 32/36 OE DQ[a,b,c,d] -75 -85 -10 Units 8.5 10 12 ns 7.5 8.5 10 ns 300 280 240 mA 120 110 100 mA 30 30 30 mA 11/8/04, v. 1.1 Alliance Semiconductor P. 1 of 18 Copyright © Alliance Semiconductor. All rights reserved. 1 page AS7C33256NTF32A AS7C33256NTF36A ® Signal descriptions Signal I/O Properties Description CLK I CLOCK Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock. CEN I SYNC Clock enable. When de-asserted high, the clock input signal is masked. A, A0, A1 I SYNC Address. Sampled when all chip enables are active and ADV/LD is asserted. DQ[a,b,c,d] I/O SYNC Data. Driven as output when the chip is enabled and OE is active. CE0, CE1, www.DataSheet4CUE.c2om ADV/LD I I SYNC SYNC Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are ignored when ADV/LD is high. Advance or Load. When sampled high, the internal burst address counter will increment in the order defined by the LBO input value. (refer to table on page 2) When low, a new address is loaded. R/W I SYNC A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE operation. Is ignored when ADV/LD is high. BW[a,b,c,d] I SYNC Byte write enables. Used to control write on individual bytes. Sampled along with WRITE command and BURST WRITE. OE I ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive. LBO Selects Burst mode. When tied to VDD or left floating, device follows Interleaved Burst I STATIC order. When driven Low, device follows linear Burst order. This signal is internally pulled High. ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused. NC - - No connects. Note that pin 84 will be used for future address expansion to 16Mb density. Snooze Mode SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state. The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ become disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successful complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly, when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. Burst Order Interleaved Burst Order LBO=1 A1 A0 A1 A0 A1 A0 Starting Address 0 0 0 1 1 0 First increment 0 1 0 0 1 1 Second increment 1 0 1 1 0 0 Third increment 1 1 1 0 0 1 A1 A0 11 10 01 00 Linear Burst Order LBO=0 A1 A0 A1 A0 A1 A0 Starting Address 0 0 0 1 1 0 First increment 0 1 1 0 1 1 Second increment 1 0 1 1 0 0 Third increment 1 1 0 0 0 1 A1 A0 11 00 01 10 11/8/04, v. 1.1 Alliance Semiconductor P. 5 of 18 5 Page Timing waveform of write cycle CLK tCENS tCENH CEN www.DataSheet4U.com Address tAS tAH A1 A2 ® tCH tCL AS7C33256NTF32A AS7C33256NTF36A tCYC A3 R/W BWn tCSS tCSH CE0,CE2 CE1 ADV/LD tADVS tADVH OE Din Dout D(A1) tHZOE Q(n-1) D(A2) D(A2Y‘01) D(A2Y‘10) tDS tDH D(A3) D(A2Y‘11) D(A3Y‘01) Command WRITE DSEL D(A1) WRITE D(A2) BURST BURST BURST WRITE WRITE WRITE D(A2Ý01) D(A2Ý10) D(A2Ý11) STALL WRITE D(A3) BURST WRITE D(A3Ý01) 11/8/04, v. 1.1 Alliance Semiconductor P. 11 of 18 11 Page

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Número de pieza	Descripción	Fabricantes
AS7C33256NTF32A	(AS7C33256NTF32A / AS7C33256NTF36A) 3.3V 256K x 2/36 Flowthrough Synchronous SRAM	Alliance Semiconductor Corporation

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