PDF AS7C331FT18A Data sheet ( Hoja de datos )

Número de pieza	AS7C331FT18A
Descripción	3.3V 1M x 18 Flow-through synchronous SRAM
Fabricantes	Alliance Semiconductor Corporation
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No Preview Available ! January 2005 AS7C331MFT18A ® 3.3V 1M x 18 Flow-through synchronous SRAM Features • Organization: 1,048,576 words x18 bits • Fast clock to data access: 6.8/7.5/8.5/10 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous flow-through operation • Asynchronous output enable control • Available 100-pin TQFP packages • Individual byte write and global write www.DataSheet4U.com • Multiple chip enables for easy expansion • 3.3 V core power supply • 2.5 V or 3.3V I/O operation with separate VDDQ • Linear or interleaved burst control • Common data inputs and data outputs • Snooze mode for reduced power-standby Logic block diagram CLK ADV ADSC ADSP A[19:0] GWE BWb BWE BWa CCEE01 CE2 ZZ OE 20 Power down LBO CLK CS Burst logic CLR D Q 20 CS Address register CLK 18 20 1M x 18 Memory array 18 18 D DQb Q BryetgeisWterriste CLK D DQa Q BryetgeisWterriste CLK D Enable Q register CE CLK D Enable Q redgeilsatyer CLK 2 OE Output buffers Input registers CLK 18 DQ[a,b] Selection guide Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) -68 -75 -85 -10 Units 7.5 8.5 10 12 ns 6.8 7.5 8.5 10 ns 285 275 250 230 mA 90 90 80 80 mA 60 60 60 60 mA 1/21/05, v 1.4 Alliance Semiconductor 1 of 19 Copyright © Alliance Semiconductor. All rights reserved. 1 page AS7C331MFT18A ® Signal descriptions Signal I/O Properties Description CLK I CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock. A,A0,A1 I SYNC Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted. DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and when OE is active. CE0 I SYNC Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the “Synchronous truth table” for more information. CE1, CE2 www.DataSheet4UA.cDoSmP I I SYNC SYNC Synchronous chip enables. Active high and active LOW, respectively. Sampled on clock edges when ADSC is active or when CE0 and ADSP are active. Address strobe processor. Asserted LOW to load a new bus address or to enter standby mode. ADSC I SYNC Address strobe controller. Asserted LOW to load a new address or to enter standby mode. ADV I SYNC Advance. Asserted LOW to continue burst read/write. GWE I SYNC Global write enable. Asserted LOW to write all 32/36 and 18 bits. When HIGH, BWE and BW[a,b] control write enable. BWE I SYNC Byte write enable. Asserted LOW with GWE HIGH to enable effect of BW[a,b] inputs. BW[a,b] I SYNC Write enables. Used to control write of individual bytes when GWE is HIGH and BWE is LOW. If any of BW[a,b] is active with GWE HIGH and BWE LOW, the cycle is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle. OE I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read mode. LBO I STATIC Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When driven LOW, device follows linear Burst order. This signal is internally pulled HIGH. ZZ I ASYNC Sleep. Places device in low power mode; data is retained. Connect to GND if unused. NC - - No connect Snooze Mode SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of SNOOZE MODE is dictated by the length of time the ZZ is in a High state. The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete. Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE. 1/21/05, v 1.4 Alliance Semiconductor 5 of 19 5 Page Key to switching waveforms ® Rising input Falling input don’t care Timing waveform of read cycle CLK tCYC tCH tCL www.DataSheet4U.com tADSPS ADSP ADSC tADSPH tADSCS tADSCH tAS tAH Address A1 A2 GWE, BWE tWS tWH tCSS CE0, CE2 tCSH LOAD NEW ADDRESS A3 CE1 ADV OE tADVS tADVH ADV inserts wait states AS7C331MFT18A Undefined Dout tOE tLZOE Q(A1) tHZOE tOH Q(A2Ý01) Q(A2Ý10) Q(A2Ý11) Q(A3) Q(A3Ý01) Q(A3Ý10) Q(A3Ý11) tCD tHZC Read Q(A1) Suspend Read Q(A1) Read Burst Burst Suspend Burst Read Burst Burst Burst Q(A2) Read Read Read Read Q(A3) Read Read Read DSEL Q(A 2Ý01) Q(A 2Ý10) Q(A 2Ý10) Q(A 2Ý11) Q(A 3Ý01) Q(A 3Ý10) Q(A 3Ý11) Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care. 1/21/05, v 1.4 Alliance Semiconductor 11 of 19 11 Page

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