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PDF AK7742 Data sheet ( Hoja de datos )
| Número de pieza | AK7742 | |
| Descripción | 24Bit 2ch ADC + 24Bit 4ch DAC | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AK7742 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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[AK7742]
= Preliminary =
AK7742
24bit 2ch ADC + 24bit 4ch DAC with Audio DSP
GENERAL DESCRIPTION
The AK7742 is a highly integrated audio digital processor, including two stereo 24bit DAC’s and one
stereo ADC with input selector. The stereo DAC and ADC feature high performance, archiving 106dB and
96dB dynamic range respectively, 8kHz to 96kHz sampling rate are supported. The audio DSP has
1536step/fs parallel processing power, and 74k-bit delay memory allows surround processing, acoustic
www.DataSheete4Uff.eccomt and parametric equalizers. As the AK7742 is a RAM based DSP, it is programmable for user
requirements. The AK7742 is available in a space saving small 48pin LQFP package.
FEATURES
■ DSP:
- Word length: 24bit (Data RAM 24bit floating point)
- Instruction cycle: 13.6 ns (1536step/fs fs=48kHz; 9216step/fs fs=8kHz)
- Multiplier 20 x 16 → 36bit (double precision available)
- Divider 20 / 20 → 20bit
- ALU: 40bit arithmetic operation (overflow margin 4bit) 24bit floating point arithmetic and
logic operation
- Program RAM: 1536 x 36bit
- Coefficient RAM: 1536 x 16bit
- Data RAM: 1536 x 24-bit (24bit floating point)
- Delay RAM: 74kbit (3072 x 24bit)
- Sampling frequency: 8kHz ~ 96kHz
- Master / Slave operation
- Serial signal input port (4ch) MSB justified 24bit / LSB justified 24 / 20 / 16bit and I2S
- Serial signal output port (6ch) MSB justified 24bit / LSB justified 24 / 16bit and I2S
■ ADC: 2ch (stereo)
- 24bit 64 x Over-sampling delta sigma (fs=8kHz~48kHz)
- DR, S/N: 96dB (fs=48kHz, fully differential input)
- S/(N+D): 84dB (fs=48kHz)
- Differential, Single-end Inputs
- Digital HPF (fc=1Hz)
- 3:1 Analog input selector
- Digital Volume (24dB~-103dB, 0.5dB Step, Mute)
■ DAC: 4ch (two stereo pairs)
- 24bit 128 x Over-sampling advanced multi-bit (fs=8kHz~96kHz)
- DR, S/N: 106dB
- S/(N+D): 92dB
- Differential output
- Digital Volume (24dB~-103dB, 0.5dB Step, Mute)
■ DSP Through Mode
■ I2C BUS interface for micro-controller
■ Power supply: +3.3V ±0.3V, internal regulator for 1.8V
■ Operating temperature range: -20°C~70°C
■ Package: 48pin LQFP (0.5mm pitch)
Rev.0.5b_PB
-1-
2008/08
1 page  
[AK7742]
PIN FUNCTION
No. Pin name
1 AIN3L
2 AIN2R
3 AIN2L
4 AVDD
5 VSS1
6 LFLT
7 TESTI
www.DataShe8et4UC.cKomM[2]
9 DVDD
10 VSS2
11 XTI
12 XTO
13 SDOUT1
14 SDIN1/JX1
15 SDIN2/JX0
16 CKM[1]
17 CKM[0]
18 IRESETN
19 I2CSEL
20 DVDD
21 VSS2
22 LRCK
23 BICK
24 CLKO/SDOUT3
25
SO/RDY/GPO/
SDOUT2
26 SDA
27 SCL
28 CAD0
29 CAD1
30 VSS1
I/O Function
Classification
I ADC Lch Single-end input 3 pin
Analog input
I ADC Rch Single-end input 2 pin
Analog input
I ADC Lch Single-end input 2 pin
Analog input
Power supply pin for analog section 3.0V ~ 3.6V
Analog power supply
Analog ground 0V
Analog power supply
O
Filter connection pin for PLL
Connect C=12nF to VSS1. “L” output during initial reset.
Analog output
I
Test pin (internal pull-down resistor)
Connect to VSS2
Test
I Clock mode select pin 2
Mode select
Power supply pin for digital section 3.0V ~ 3.6V
Digital power supply
Digital ground 0V
Digital power supply
Master clock input pin
I When using a crystal oscillator, connect it between this pin and XTO. Clock
When using external main clock, input to this pin with CMOS level.
Crystal oscillator output pin
O
When
When
using a crystal oscillator, connect it between this pin and XTI.
not using crystal oscillator, leave open. Output during initial reset
is
Clock
not determined.
O DSP serial data output pin
“L” output during initial reset
Data interface
I Serial data input pin 1 / JX1
Data interface
I Serial data input pin 2 / JX0
Data interface
I Clock mode select pin 1
Mode select
I Clock mode select pin 0
Mode select
I Reset pin (for initialization)
Reset
I
I2CBUS select pin
Connect to DVDD
Microcomputer I/F
Power supply pin for digital section 3.0V ~ 3.6V
Digital power supply
Digital ground 0V
Digital power supply
I/O LR channel select clock pin
“L” output during initial reset with master mode.
Data interface
I/O Serial bit clock pin
“L” output during initial reset with master mode.
Data interface
O Clock output / DSP serial data output pin
“L” output during initial reset
Clock
Serial data output pin / Data write ready output pin / General purpose output
O / DSP serial data output pin
Microcomputer I/F
“L” output during initial reset
I/O SDA I2C bus interface
I SCL I2C bus interface
Microcomputer I/F
Microcomputer I/F
I I2C bus address pin 0
I I2C bus address pin 1
Microcomputer I/F
Microcomputer I/F
Analog ground 0V
Analog power supply
Rev.0.5b_PB
-5-
2008/08
5 Page 
[AK7742]
SWITCHING CHARACTERISTICS
■ System Clock
(Ta=-20ºC~70ºC; AVDD=DVDD=3.0~3.6V)
Parameter
Symbol
XTI
a)with a crystal oscillator
Frequency(256fs)
CKM[2:0]= 000
fs=44.1KHz fXTI
fs=48KHz
www.DataSheet4U.com
CKM[2:0]= 001
fXTI
b)with an external clock
Duty cycle
Frequency(256fs)
fs=44.1KHz
CKM[2:0]= 000, 010
fs=48KHz
Frequency (384fs)
fs=44.1KHz
CKM[2:0]= 001
fs=48KHz
LRCK frequency (Note 23)
Duty
fXTI
fXTI
Fs
min
-
-
40
11.0
16.5
7.35
typ
11.2896
12.288
16.9344
18.432
50
11.2896
12.288
16.9344
18.432
48
max Unit
- MHz
- MHz
60 %
12.4 MHz
18.6 MHz
96 kHz
BICK frequency
a) CKM[2:0]= 001, 010
32 64
fs
High level width
Low level width
Frequency
tBCLKH
tBCLKL
fBCLK
64
64
0.46
3.072
6.144
ns
ns
MHz
b) CKM[2:0]= 011 (Note 25)
64 fs
Duty cycle
Frequency
Duty
40 50
fBCLK 2.75 3.072
60 %
3.1 MHz
c) CKM[2:0]= 100 (Note 26)
Duty cycle
Frequency
Duty
fBCLK
40
230
32
50
256
fs
60 %
258 kHz
d) CKM[2:0]= 101 (Note 27)
Duty cycle
Frequency
Duty
fBCLK
40
460
64
50
512
fs
60 %
516 kHz
Note 23. LRCK frequency and sampling rate (fs) should be the same.
Note 24. The BICK must be divided 32, 48 or 64 clocks correctly. (BICK can be selected from 32fs, 48fs or 64fs)
Note 25. When BICK is resource of internal MCLK. The BICK must be divided 64 clocks correctly. 64fs fixed.
Note 26. When BICK is resource of internal MCLK. The BICK must be divided 32 clocks correctly. 32fs fixed.
Note 27. When BICK is resource of internal MCLK. The BICK must be divided 64 clocks correctly. 64fs fixed.
Rev.0.5b_PB
- 11 -
2008/08
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AK7742.PDF ] | |
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