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PDF LM3S1110 Data sheet ( Hoja de datos )

Número de pieza LM3S1110
Descripción Microcontroller
Fabricantes Luminary　
Logotipo Luminary Logotipo



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No Preview Available ! LM3S1110 Hoja de datos, Descripción, Manual

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PRELIMINARY
LM3S1110 Microcontroller
DATA SHEET
D S - L M 3 S 111 0 - 1 5 8 2
Copyright © 2007 Luminary Micro, Inc.

1 page




LM3S1110 pdf
LM3S1110 Microcontroller
10 General-Purpose Timers ................................................................................................. 185
10.1 Block Diagram ........................................................................................................................ 186
10.2 Functional Description ............................................................................................................. 186
10.2.1 GPTM Reset Conditions .......................................................................................................... 186
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 186
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 188
10.3 Initialization and Configuration ................................................................................................. 192
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 192
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 193
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 193
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 194
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 194
www.DataSheet4U1.0c.o3m.6 16-Bit PWM Mode ................................................................................................................... 195
10.4 Register Map .......................................................................................................................... 195
10.5 Register Descriptions .............................................................................................................. 196
11 Watchdog Timer ............................................................................................................... 221
11.1 Block Diagram ........................................................................................................................ 221
11.2 Functional Description ............................................................................................................. 221
11.3 Initialization and Configuration ................................................................................................. 222
11.4 Register Map .......................................................................................................................... 222
11.5 Register Descriptions .............................................................................................................. 223
12 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 244
12.1 Block Diagram ........................................................................................................................ 245
12.2 Functional Description ............................................................................................................. 245
12.2.1 Transmit/Receive Logic ........................................................................................................... 245
12.2.2 Baud-Rate Generation ............................................................................................................. 246
12.2.3 Data Transmission .................................................................................................................. 247
12.2.4 Serial IR (SIR) ......................................................................................................................... 247
12.2.5 FIFO Operation ....................................................................................................................... 248
12.2.6 Interrupts ................................................................................................................................ 248
12.2.7 Loopback Operation ................................................................................................................ 249
12.2.8 IrDA SIR block ........................................................................................................................ 249
12.3 Initialization and Configuration ................................................................................................. 249
12.4 Register Map .......................................................................................................................... 250
12.5 Register Descriptions .............................................................................................................. 251
13 Synchronous Serial Interface (SSI) ................................................................................ 285
13.1 Block Diagram ........................................................................................................................ 285
13.2 Functional Description ............................................................................................................. 285
13.2.1 Bit Rate Generation ................................................................................................................. 286
13.2.2 FIFO Operation ....................................................................................................................... 286
13.2.3 Interrupts ................................................................................................................................ 286
13.2.4 Frame Formats ....................................................................................................................... 287
13.3 Initialization and Configuration ................................................................................................. 294
13.4 Register Map .......................................................................................................................... 295
13.5 Register Descriptions .............................................................................................................. 296
14 Analog Comparators ....................................................................................................... 322
14.1 Block Diagram ........................................................................................................................ 322
September 02, 2007
Preliminary
5

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LM3S1110 arduino
LM3S1110 Microcontroller
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
www.DataSheet4UR.ecogmister 15:
Register 16:
Register 17:
Register 18:
Flash Memory Control (FMC), offset 0x008 ..................................................................... 128
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 130
Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 131
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 132
USec Reload (USECRL), offset 0x140 ............................................................................ 133
Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 134
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 135
User Debug (USER_DBG), offset 0x1D0 ......................................................................... 136
User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 137
User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 138
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 139
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 140
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 141
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 142
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 143
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 144
General-Purpose Input/Outputs (GPIOs) ................................................................................... 145
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 151
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 152
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 153
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 154
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 155
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 156
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 157
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 158
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 159
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 160
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 162
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 163
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 164
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 165
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 166
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 167
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 168
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 169
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 170
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 171
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 173
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 174
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 175
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 176
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 177
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 178
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 179
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 180
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 181
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 182
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 183
September 02, 2007
Preliminary
11

11 Page







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