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PDF ICS8344I-01 Data sheet ( Hoja de datos )
| Número de pieza | ICS8344I-01 | |
| Descripción | 1-TO-24 DIFFERENTIAL -TO-LVCMOS/LVTTL FANOUT BUFFER | |
| Fabricantes | Integrated Device Technology | |
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PRELIMINARY
LOW SKEW, 1-TO-24 DIFFERENTIAL-
TO-LVCMOS/LVTTL FANOUT BUFFER
ICS8344I-01
GENERAL DESCRIPTION
The ICS8344I-01 is a low voltage, low skew
ICS fanout buffer and a member of the HiPerClockS ™
HiPerClockS™ family of High Performance Clock Solutions from
IDT. The ICS8344I-01 has two selectable clock in-
puts. The CLKx, nCLKx pairs can accept most
standard differential input levels. The ICS8344I-01 is designed
to translate any differential signal level to LVCMOS/LVTTL lev-
els. The low impedance LVCMOS/LVTTL outputs are designed
www.DatatSohederti4vUe.c5o0mΩ series or parallel terminated transmission lines.
The effective fanout can be increased to 48 by utilizing the
ability of the outputs to drive two series terminated lines.
Redundant clock applications can make use of the dual clock
inputs which also facilitate board level testing. The clock
enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the
clock enable pin. The outputs are driven low when disabled.
The ICS8344I-01 is characterized at full 3.3V, full 2.5V and
mixed 3.3V input and 2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics make
the ICS8344I-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
FEATURES
• Twenty-four LVCMOS/LVTTL outputs,
7Ω typical output impedance
• Two selectable differential CLKx, nCLKx inputs
• CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the
following input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 200MHz
• Translates any single ended input signal to LVCMOS/LVTTL
with resistor bias on nCLK input
• Synchronous clock enable
• Output skew: 250ps (maximum)
• Part-to-part skew: 1ns (maximum)
• Bank skew: 125ps (maximum)
• Propagation delay: 5.25ns (maximum)
• Output supply modes:
Core/Output
3.3V/3.3V
2.5V/2.5V
3.3V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
0
1
CLK_EN
LE
Q
nD
Q0:Q7
Q8:Q15
Q16:Q23
Q16
Q17
VDDO
GND
Q18
Q19
Q20
Q21
VDDO
GND
Q22
Q23
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 ICS8344-01 33
5
48-Lead LQFP
32
6 7mm x 7mm x 1.4mm 31
7
8
9
10
package body
Y Package
Top View
30
29
28
27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
Q7
Q6
VDDO
GND
Q5
Q4
Q3
Q2
VDDO
GND
Q1
Q0
OE
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
1
ICS8344AYI-01 REV. B MAY 10, 2007
1 page  
ICS8344I-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PRELIMINARY
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5% OR 2.5V ± 5%, OR VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%;
TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
I
IH
Input
nCLK0, nCLK1
High Current CLK0, CLK1
VDD = VIN = 3.465V or 2.625V
VDD = VIN = 3.465V or 2.625V
5 µA
150 µA
IIL
Input
nCLK0, nCLK1 VDD = 3.465V or 2.625V, VIN = 0V
Low Current CLK0, CLK1
VDD = 3.465V or 2.625V, VIN = 0V
-150
-5
µA
µA
VPP Peak-to-Peak Input Voltage
0.15 1.3
VCMR
Common Mode Input Voltage:
NOTE 1, 2
GND + 0.5
VDD - 0.85
www.DataSNheOeTt4EU1.c:oFmor single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
V
V
TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5% OR 2.5V ± 5%, OR VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%;
TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tPD
tsk(b)
Output Frequency
Propagation Delay, NOTE 1
Q0:Q7
Bank Skew;
NOTE 2, 6
Q8:Q15
Q16:Q23
f ≤ 200MHz
Measured on the rising edge of VDDO/2
2.5
200
5.25
125
200
175
MHz
ns
ps
ps
ps
tsk(o)
tsk(pp)
tR
tF
odc
Output Skew; NOTE 3, 6
Part-to-Part Skew; NOTE 4, 6
Output Rise Time; NOTE 5
Output Fall Time; NOTE 5
Output Duty Cycle
Measured on the rising edge of VDDO/2
Measured on the rising edge of VDDO/2
30% to 70%
30% to 70%
f ≤ 200MHz
200
200
40%
250
1
800
800
60%
ps
ns
ps
ps
%
tEN Output Enable Time; NOTE 5
f = 10MHz
5 ns
tDIS Output Disable TIme; NOTE 5
f = 10MHz
4 ns
All parameters measured at 200MHz and VPPtyp unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to VDDO/2.
NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
5
ICS8344AYI-01 REV. B MAY 10, 2007
5 Page 
ICS8344I-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP
www.DataSheet4U.com
PRELIMINARY
TABLE 7. PACKAGE DIMENSIONS
SYMBOL
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
MINIMUM
NOMINAL
N 48
A -- --
A1 0.05
--
A2 1.35 1.40
b 0.17 0.22
c 0.09 --
D 9.00 BASIC
D1 7.00 BASIC
D2 5.50 Ref.
E 9.00 BASIC
E1 7.00 BASIC
E2 5.50 Ref.
e 0.50 BASIC
L 0.45 0.60
θ 0° --
ccc --
--
Reference Document: JEDEC Publication 95, MS-026
MAXIMUM
1.60
0.15
1.45
0.27
0.20
0.75
7°
0.08
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
11
ICS8344AYI-01 REV. B MAY 10, 2007
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ICS8344I-01.PDF ] | |
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