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PDF LMV1088 Data sheet ( Hoja de datos )
| Número de pieza | LMV1088 | |
| Descripción | Far Field Noise Suppression Microphone Amplifier | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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December 10, 2007
LMV1088
Dual Input, Far Field Noise Suppression Microphone
Amplifier with Automatic Calibration Ability
General Description
The LMV1088 is a fully analog dual input microphone array
amplifier designed to reduce background acoustic noise,
while delivering superb speech clarity in voice communica-
tions applications.
The LMV1088 incorporates calibration circuitry which may be
www.DataSheeitn4iUtia.cteodmby either an I2C command or by a logic level control
on a separate input pin. The calibration sequence compen-
sates for gain and frequency response variations of the mi-
crophones used with the LMV1088, eliminating the need to
use expensive matched microphone sets. The calibration da-
ta is stored in the internal EEPROM memory. The LMV1088
has two differential input microphone amplifier channels plus
far field noise suppression (FFNS) processing circuitry. The
amplifiers and FFNS circuitry are adjustable for gain differ-
ences in the MIC channels of +/- 3dB. The frequency re-
sponse variations of the microphones over the voice band
frequency range can also be adjusted for differences of
+/-3dB.
The compensation or calibration function is achieved via
memory stored coefficients. These are determined when the
FFNS calibration fuction is activated. The purpose of the cal-
ibration sequence is to choose the optimized coefficients for
the FFNS circuitry for the given microphones, spacing, and
acoustical environment.
Key Specifications
(3.3V supply, unless otherwise specified)
■ Supply voltage
■ Supply current
■ Signal to noise ratio (A-weighted)
■ Total harmonic distortion (A-weighted)
■ Temperature range
2.7V to 5.5V
1mA (typ)
60dB (typ)
0.1% (typ)
−40°C to 85°C
Features
■ Low power consumption
■ Neglectable noise suppression processing delay
■ Automatic Calibration
■ Three microphone usage modes
■ Space-saving 36 Bump micro SMD package
Applications
■ Cellular phones
■ Mobile and handheld two-way radios
■ Bluetooth and other powered headsets
Application of the LMV1088
20213040
© 2007 National Semiconductor Corporation 202130
www.national.com
1 page  
Absolute Maximum Ratings (Note 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Storage Temperature
ESD Rating (Note 6)
ESD Rating (Note 7)
Junction Temperature (TJMAX)
Mounting Temperature
Infrared or Convection (20 sec.)
6.0V
-85°C to +150°C
2000V
200V
150°C
235°C
Thermal Resistance
θJA (microSMD)
70°C/W
Soldering Information See AN-112 “microSMD Wafers Level
Chip Scale Package.”
Operating Ratings (Note 4)
Supply Voltage
I2CVDD (Note 12)
Temperature Range
2.7V to 5.5V
1.8V to 5.5V
−40°C to 85°C
Electrical Characteristics 3.3V (Note 3)
Unless otherwise specified, all limits guaranteed for TJ = 25°C, VDD = 3.3V, VIN = 18mVPP, pass through mode (Note 10), preamplifier
gain = 20 dB, postamplifier gain = -2.5dB, RL = 100kΩ, and CL = 4.7pF.
www.DataSheet4U.com
Symbol
Parameter
Conditions
LMV1088
Units (Limits)
Typical (Note 8) Limits (Note 9)
SNR
VIN
Vout
Signal-to-Noise Ratio
Max Input Signal
AC Output Voltage
DC Output Voltage
f = 1kHz, , VIN = 18mVPP, A-Weighted
f = 1kHz and THD+N < 1%
f = 1kHz
60
97
500
800
dB
mVPP
mVRMS
mV
THD+N Total Harmonic Distortion + Noise
f = 1kHz, VIN = 18mVPP
ZIN Input Impedance
ZOUT Output Impedance
ZLOAD
RLOAD
CLOAD
A Microphone Pre Amplifier Gain Range f = 1kHz
M
A Microphone Pre Amplifier Gain
MR Adjustment Resolution
f = 1kHz
0.1
100
150
6 – 36
2
%
kΩ
Ω
10 kΩ (min)
10 pF (max)
dB
dB
AP Post Amplifier Gain Range
f = 1kHz Pass Through Mode and
Summing Mode
f = 1kHz Noise Cancelling Mode
(Note 11)
-2.5 – 9.5
0 – 12
dB
dB
APR
Post Amplifier Gain Adjustment
Resolution
f = 1kHz
3 dB
ACR Gain Compensation Range
AMD
Gain Matching Difference After
Calibration
f = 300Hz — f = 3400Hz
f = 300Hz
f = 1kHz
f = 3kHz
±3 dB (max)
0.5 dB (max)
0.5 dB (max)
0.5 dB (max)
TCAL Calibration Duration
Input Referred, Input AC grounded
770 ms (max)
PSRR Power Supply Rejection Ratio
CMRR Common Mode Rejection Ratio
f = 217Hz (100mVPP)
f = 1kHz (100mVPP)
f = 1kHz,
85
80
60
dB
dB
dB
V
BM
εVBM
IBM
Microphone Bias Supply Voltage
Microphone Bias Supply Noise
Total available Microphone Bias
Current
IBIAS = 1mA
A-Weighted
2.0 V
10 μVRMS
1.2 mA (min)
IDDQ
IDDCP
Supply Quiescence Current
VIN = 0V
Supply Current during Calibration and Calibrating or Programming
Programming
EEPROM
1 1.5 mA (max)
28 50 mA (max)
IDD Supply Current
Vin = 25mVPP both inputs, Noise
canceling mode
1
1.5 mA (max)
5 www.national.com
5 Page 
Application Data
I2C Compatible Interface
nals need a pull-up resistor according to I2C specification. The
LMV1088 can be controlled on two slave addresses depend-
ing on the logical level at the I2C address pin. The two I2C
slave address for LMV1088 are given inTable 2 .
I2C SIGNALS
The LMV1088 pin SCL is used for the I2C clock SCL and the
pin SDA is used for the I2C data signal SDA. Both these sig-
TABLE 2. Chip Address
1st Chip Address
I2C Adress='0'
2nd Chip Address
I2C Adress='1'
D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 0 1 1 0 W/R
1 1 0 0 1 1 1 W/R
www.DataIS2CheDeAt4TUA.coVmALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data line
can only be changed when SCL is LOW.
I2C Signals: Data Validity
202130q1
I2C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I2C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from LOW
to HIGH while SCL is HIGH. The I2C master always generates
START and STOP bits. The I2C bus is considered to be busy
after START condition and free after STOP condition. During
data transmission, I2C master can generate repeated START
conditions. First START and repeated START conditions are
equivalent, function-wise.(Note 13)
Note 13: The master should issue STOP after no acknowledgement.
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac-
knowledge clock pulse. The receiver must pull down the SDA
line during the 9th clock pulse, signifying an acknowledge. A
receiver which has been addressed must generate an ac-
knowledge after each byte has been received.
After the START condition, the I2C master sends a chip ad-
dress. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). The LMV1088 address
is 110011002or 110011102. For the eighth bit, a “0” indicates
a WRITE and a “1” indicates a READ. The second byte se-
lects the register to which the data will be written. The third
byte contains data to write to the selected register.
I2C Chip Address
202130q3
Register changes take effect at the SCL rising edge during
the last ACK from slave.
In Figure 2 there is a write example shown, for a device at a
random chosen address'001101002'.
I2C Start Stop Conditions
202130q2
11 www.national.com
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet LMV1088.PDF ] | |
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