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PDF LH5164AZ8 Data sheet ( Hoja de datos )
| Número de pieza | LH5164AZ8 | |
| Descripción | CMOS 64K (8K x 8) Static RAM | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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LH5164AZ8
FEATURES
• 8,192 × 8 bit organization
• Access time:
200 ns (VCC = 3.0 V MAX.)
• Power consumption:
Operating:
60 mW (MAX.) @ 3 V
Standby (to 60°C):
3 µW (MAX.) @ 3 V
Data hold
0.6 µA (VCC = 3 V, TA = 60°C)
• Operating voltage range:
3.0 V to 3.6 V
• Wide operating temperature range:
-30 to 60°C
• Fully-static operation
• TTL compatible I/O
• Three-state outputs
• Package: 28-pin, 450-mil SOP
CMOS 64K (8K × 8) Static RAM
DESCRIPTION
The LH5164AZ8 is a static RAM organized as
8,192 × 8 bits. It is fabricated using silicon-gate CMOS
process technology.
PIN CONNECTIONS
28-PIN SOP
TOP VIEW
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 WE
26 CE2
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE1
19 I/O8
18 I/O7
17 I/O6
16 I/O5
15 I/O4
5164AZ8-1
Figure 1. Pin Connections for SOP Package
1
1 page  
CMOS 64K (8K × 8) Static RAM
LH5164AZ8
DATA RETENTION CHARACTERISTICS (TA = -30 to +60°C)
PARAMETER
SYMBOL
CONDITIONS
Data retention supply voltage
Data retention supply current
VCCDR
ICCDR
CE2 ≤ 0.2 V or
CE1 ≥ VCCDR – 0.2 V
VCCDR = 3.0 V,
CE2 ≤ 0.2 V or
CE1 ≥ VCCDR – 0.2 V
TA = 25°C
TA = 60°C
Chip disable to data retention
tCDR
Recovery time
tR
NOTES:
1. CE2 should be ≥ VCCDR - 0.2 V or ≤ 0.2 V.
2. tRC = Read cycle time
MIN.
2.0
0
tRC
MAX.
5.5
0.2
0.6
UNIT NOTE
V1
µA
1
ns
ns 2
ADDRESS
CE1
tRC
tAA
tACE1
tLZ1
tACE2
tHZ1
CE2
tLZ2
tOE
tOLZ
tHZ2
OE
tOHZ
tOH
DOUT
NOTE: WE is "HIGH" level during the read cycle.
DATA VALID
Figure 3. Read Cycle
5164AZ8-3
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet LH5164AZ8.PDF ] | |
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