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PDF PI74ALVCH16374 Data sheet ( Hoja de datos )
| Número de pieza | PI74ALVCH16374 | |
| Descripción | 16-Bit Edge Triggered D-Type Flip-Flop | |
| Fabricantes | Pericom Semiconductor Corporation | |
| Logotipo |  |
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PI74ALVCH16374
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16-Bit Edge Triggered D-Type Flip-Flop
with 3-State Outputs
Product Features
• PI74ALVCH16374 is designed for low voltage operation
• VCC = 2.3V to 3.6V
• Hysteresis on all inputs
• Typical VOLP (Output Ground Bounce)
www.DataShe<et04U.8.cVomat VCC = 3.3V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
• Bus Hold retains last active bus state during 3-STATE
eliminating the need for external pullup resistors
• Industrial operation at 40°C to +85°C
• Packages available:
48-pin 240 mil wide plastic TSSOP (A)
48-pin 300 mil wide plastic SSOP (V)
Logic Block Diagram
1OE 1
1CLK 48
47
1D1
C1
1D
2 1Q1
Product Description
Pericom Semiconductors PI74ALVCH series of logic circuits are
produced in the Companys advanced 0.5 micron CMOS technology,
achieving industry leading speed.
This 16-bit edge-triggered D-type flip-flop is designed for 2.3V to
3.6V VCC operation.
The PI74ALVCH16374 is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working
registers. This device can be used as two 8-bit flip-flops or one
16-bit flip-flop. On the positive transition of the Clock (CLK)
input, the Q outputs of the flip-flop take on the logic levels set up
at the data (D) inputs. OE can be used to place the eight outputs in
either a normal logic state (high or low logic levels) or a high-
impedance state. In that state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased
drive provide the capability to drive bus lines without need for
interface or pullup components. OE does not affect internal
operations of the flip-flop. Old data can be retained or new data can
be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
24
2OE
2CLK 25
36
2D1
To Seven Other Channels
C1
1D
13 2Q1
To Seven Other Channels
1
PS8138A 09/03/98
1 page  
PI74ALVCH16374
16-Bit Edge Triggered D-Type Flip-Flop
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Switching Characteristics over Operating Range(1)
Parameters
From (INPUT)
VCC = 2.5V ±0.2V
To (OUTPUT)
Min.(2) Max.
fMAX
150
tPD CLK
1.0 5.3
tEN OE
Q 1.0 6.2
www.DataSheet4UtD.cIoSm
Notes:
OE
1.7
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
5.3
VCC = 2.7V
Min. Max.
150
4.9
5.9
4.7
VCC = 3.3V ±0.3V
Min.(2) Max.
150
1.0 4.2
1.0 4.8
1.0 4.3
Units
MHz
ns
Operating Characteristics, TA = 25ºC
Parameter
CPD Power Dissipation
Capacitance
Outputs Enabled
Outputs Disabled
Test Conditions
CL = 50pF, f = 10 MHz
VCC = 2.5V ±0.2V VCC = 3.3V ±0.3V
Typ.
31 30
16 18
Units
pF
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
5 PS8138A 09/03/98
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet PI74ALVCH16374.PDF ] | |
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