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PDF PI74ALVCH16344 Data sheet ( Hoja de datos )

Número de pieza PI74ALVCH16344
Descripción 1-Bit to 4-Bit Address/Driver
Fabricantes Pericom Semiconductor Corporation 
Logotipo Pericom Semiconductor Corporation Logotipo



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PI74ALVCH16344
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1-Bit to 4-Bit Address/Driver
with 3-State Outputs
Product Features
PI74ALVCH16344 is designed for low voltage operation
VCC = 2.3V to 3.6V
Hysteresis on all inputs
Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
www.DataSheTeyt4pUic.caolmVOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
Industrial operation at –40°C to +85°C
Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced in the Company’s advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The PI74ALVCH16344 is a 1-bit to 4-bit buffer/driver designed for
2.3V to 3.6V Vcc operation.
The address/driver is designed for applications where four seperate
memory locations must be addressed by a single address.
To ensure the high-impedance state during power up or power down,
OE should be tied to VCC through a pullup resistor; the minimum
value of the resistor is determined by the current-sinking capability
of the driver.
The PI74ALVCH16344 has “Bus Hold” which retains the data
input’s last state whenever the data input goes to high-impedance
preventing “floating” inputs and eliminating the need for pullup/
down resistors.
Logic Block Diagram
OE1 1
A1 8
2 B11
6 B14
OE3 29
A5 36
34 B51
30 B54
A2 14
9 B21
13
B24
A6 42
41 B61
37 B64
28
OE2
15
A3
A4 21
16 B31
20 B34
23 B41
27 B44
56
OE4
A7 43
A8 49
48 B71
44 B74
55 B81
51 B84
1 PS8166B 10/19/99

1 page




PI74ALVCH16344 pdf
PI74ALVCH16344
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Switching Characteristics over Operating Range(1)
Parameters
From
(INPUT)
To VCC = 2.5V ± 0.2V
(OUTPUT) Min.(2) Max.
VCC = 2.7V VCC = 3.3V ± 0.3V
Min.(2) Max. Min.(2) Max.
tPD A
B 1.0 5.0
tEN OE B 1.0 6.8
tDIS OE B 1.0 6.0
tsk(0)(3)
tsk(0)(4)
4.0 1.0
3.6
6.0 1.0
5.0
5.2 1.0
5.0
- 0.35
- 0.5
Notes:
www.DataS1h.eSete4eUt.ceostmcircuit and waveforms, Figures 1 and 2.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between outputs of same bank, and same device and same transition.
This parameter is warranted but not production tested.
4. Skew between outputs of all banks, and same device, A1-A8 tied together.
This parameter is warranted but not production tested.
Units
ns
Operating Characteristics, TA = 25ºC
Parameter
Test Conditions
CPD Power Dissipation Outputs Enabled
Capacitance
Outputs Disabled
CL = 50pF,
f = 10 MHz
VCC = 2.5V
± 0.2V
VCC = 3.3V ±
0.3V
Typical
68 84
11 14
Units
pF
5 PS8166B 10/19/99

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