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PDF ADL5371 Data sheet ( Hoja de datos )
| Número de pieza | ADL5371 | |
| Descripción | 500 MHz to 1500 MHz Quadrature Modulator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Output frequency range: 500 MHz to 1500 MHz
Modulation bandwidth: >500 MHz (3 dB)
1 dB output compression: 14.4 dBm @ 900 MHz
Noise floor: −158.6 dBm/Hz @ 915 MHz
Sideband suppression: −55 dBc @ 900 MHz
Carrier feedthrough: −50 dBm @ 900 MHz
www.DataSheeSt4inUg.cleomsupply: 4.75 V to 5.25 V
24-lead LFCSP
APPLICATIONS
Cellular communication systems at 900 MHz
CDMA2000/GSM
WiMAX/broadband wireless access systems
Cable communication equipment
Satellite modems
GENERAL DESCRIPTION
The ADL5371 is a member of the fixed-gain quadrature modulator
(F-MOD) family designed for use from 500 MHz to 1500 MHz.
Its excellent phase accuracy and amplitude balance enable high
performance intermediate frequency or direct radio frequency
modulation for communication systems.
The ADL5371 provides a >500 MHz, 3 dB baseband bandwidth,
making it ideally suited for use in broadband zero IF or low IF-
to-RF applications and in broadband digital predistortion
transmitters.
500 MHz to 1500 MHz
Quadrature Modulator
ADL5371
FUNCTIONAL BLOCK DIAGRAM
IBBP
IBBN
LOIP
LOIN
QUADRATURE
PHASE
SPLITTER
VOUT
QBBN
QBBP
Figure 1.
The ADL5371 accepts two differential baseband inputs and
a single-ended local oscillator (LO) and generates a single-
ended output.
The ADL5371 is fabricated using the Analog Devices, Inc.
advanced silicon-germanium bipolar process. It is available in a
24-lead, exposed-paddle, Pb-free, LFCSP. Performance is specified
over a −40°C to +85°C temperature range. A Pb-free evaluation
board is available.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADL5371
COM1 1
COM1 2
VPS1 3
VPS1 4
VPS1 5
VPS1 6
F-MOD
TOP VIEW
(Not to Scale)
18 VPS5
17 VPS4
16 VPS3
15 VPS2
14 VPS2
13 VOUT
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Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2
COM1
Input Common Pins. Connect to ground plane via a low impedance path.
7, 10 COM2
Input Common Pins. Connect to ground plane via a low impedance path.
11, 12
COM3
Input Common Pins. Connect to ground plane via a low impedance path.
21, 22
COM4
Input Common Pins. Connect to ground plane via a low impedance path.
3 to 6
VPS1
Positive Supply Voltage Pins. All pins should be connected to the same supply (VS). To ensure
adequate external bypassing, connect 0.1 μF capacitors between each pin and ground.
Adjacent power supply pins of the same name can share one capacitor (see Figure 23).
14, 15
VPS2
Positive Supply Voltage Pins. All pins should be connected to the same supply (VS). To ensure
adequate external bypassing, connect 0.1 μF capacitors between each pin and ground.
Adjacent power supply pins of the same name can share one capacitor (see Figure 23).
16 to 18
VPS3 to VPS5
Positive Supply Voltage Pins. All pins should be connected to the same supply (VS). To ensure
adequate external bypassing, connect 0.1 μF capacitors between each pin and ground.
Adjacent power supply pins of the same name can share one capacitor (see Figure 23).
8, 9
LOIP, LOIN
50 Ω Single-Ended Local Oscillator Input. Internally dc-biased. Pins must be ac-coupled.
AC-couple LOIN to ground and drive LO through LOIP.
13
VOUT
Device Output. Single-ended RF output. Pin should be ac-coupled to the load. The output is
ground referenced.
19, 20, 23, 24
IBBP, IBBN,
QBBN, QBBP
Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs must be
dc-biased to 500 mV dc and must be driven from a low impedance source. Nominal characterized
ac signal swing is 700 mV p-p on each pin. This results in a differential drive of 1.4 V p-p with a
500 mV dc bias. These inputs are not self-biased and must be externally biased.
Exposed Paddle Connect to ground plane via a low impedance path.
Rev. 0 | Page 5 of 20
5 Page 
BASIC CONNECTIONS
Figure 23 shows the basic connections for the ADL5371.
QBBP
QBBN IBBN
IBBP
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COM1 1
COM1 2
VPS1 3
VPS1 4
VPS1 5
VPS1 6
C12
0.1µF
Z1
F-MOD
EXPOSED PADDLE
C16
0.1µF
C15
0.1µF
18 VPS5
17 VPS4
16 VPS3
15 VPS2
14 VPS2
C14
0.1µF
VPOS
13
VOUT
C13
0.1µF
COUT
100pF
C11
OPEN
VOUT
GND
CLOP
100pF
LO
CLON
100pF
Figure 23. Basic Connections for the ADL5371
POWER SUPPLY AND GROUNDING
All the VPS pins must be connected to the same 5 V source.
Adjacent pins of the same name can be tied together and decoupled
with a 0.1 μF capacitor. These capacitors should be located as
close as possible to the device. The power supply can range
between 4.75 V and 5.25 V.
The COM1 pin, COM2 pin, COM3 pin, and COM4 pin should
be tied to the same ground plane through low impedance paths.
The exposed paddle on the underside of the package should also
be soldered to a low thermal and electrical impedance ground
plane. If the ground plane spans multiple layers on the circuit
board, they should be stitched together with nine vias under the
exposed paddle. The Application Note AN-772 discusses the
thermal and electrical grounding of the LFCSP in detail.
ADL5371
BASEBAND INPUTS
The baseband inputs QBBP, QBBN, IBBP, and IBBN must be
driven from a differential source. The nominal drive level of
1.4 V p-p differential (700 mV p-p on each pin) should be
biased to a common-mode level of 500 mV dc.
The dc common-mode bias level for the baseband inputs range
from 400 mV to 600 mV. This results in a reduction in the
usable input ac swing range. The nominal dc bias of 500 mV
allows for the largest ac swing, limited on the bottom end by the
ADL5371 input range and on the top end by the output compliance
range on most DACs from Analog Devices.
LO INPUT
A single-ended LO signal should be applied to the LOIP pin
through an ac coupling capacitor. The recommended LO drive
power is 0 dBm. The LO return pin, LOIN, should be ac-coupled
to ground through a low impedance path.
The nominal LO drive of 0 dBm can be increased to up to 7 dBm
to realize an improvement in the noise performance of the
modulator (see Figure 33). This improvement is tempered by
degradation in the sideband suppression performance (see
Figure 19) and, therefore, should be used judiciously. If the LO
source cannot provide the 0 dBm level, operation at a reduced
power below 0 dBm is acceptable. Reduced LO drive results in
slightly increased modulator noise. The effect of LO power on
sideband suppression and carrier feedthrough is shown in
Figure 19. The effect of LO power on GSM noise is shown in
Figure 33.
RF OUTPUT
The RF output is available at the VOUT pin (Pin 13). The
VOUT pin connects to an internal balun, which is capable of
driving a 50 Ω load. For applications requiring 50 Ω output
impedance, external matching is needed (see Figure 8 for S22
performance). The internal balun provides a low dc path to
ground. In most situations, the VOUT pin should be ac-coupled
to the load.
Rev. 0 | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADL5371.PDF ] | |
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