PDF PI6CVF857 Data sheet ( Hoja de datos )

Número de pieza	PI6CVF857
Descripción	1:10 PLL Clock Driver
Fabricantes	Pericom Semiconductor Corporation
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No Preview Available ! PI6CVF857 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory Product Features • Operating Frequency up to 220 MHz for PC3200 Registered DIMM applications • Distributes one differential clock input pair to ten differential clock output pairs • Inputs(CLK,CLK)and(FBIN,FBIN) www.DataS•hIenept4uUt .PcoWmRDWN: LVCMOS • Outputs (Yx,Yx),(FBOUT,FBOUT) • External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the clock input • Operatesat2.5VforPC1600,PC2100,PC2700, and 2.6V for PC3200 • Packaging (Pb-free & Green available, select packages): – 48-pin TSSOP – 40-pin TQFN – 56-ball VFBGA Block Diagram CLK CLK FBIN FBIN PLL PWRDWN AVDD Powerdown and Test Logic Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 FBOUT FBOUT Product Description PI6CVF857 PLL clock device is developed for registered DDR DIMM applications. The device is a zero-delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]), and one differential pair feedback clock outputs (FBOUT,FBOUT) . The clock outputs are controlled by the input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V LVCMOS input (PWRDWN), and the Analog Power input (AVDD). When input PWRDWN is low while power is applied, the input receivers are disabled, the PLL is turned off, and the differential clock outputs are 3-stated. When the AVDD is strapped low, the PLL is turned off and bypassed for test purposes. When the input frequency falls below a suggested detection fre- quency that is below the operating frequency of the PLL, the device will enter a low power mode. An input frequency detection circuit will detect the low frequency condition and perform the same low power features as when the PWRDWN input is low. The PLL in the PI6CVF857 clock driver uses the input clocks (CLK, CLK) and the feedback clocks (FBIN,FBIN) to provide high-perfor- mance, low-skew, low-jitter output differential clocks (Y[0:9], Y[0:9]). The PI6CVF857 is also able to track Spread Spectrum Clocking for reduced EMI. 1 PS8683B 10/17/03 1 page PI6CVF857 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122 Timing Requirements for PC1600 ~ PC2700 (Over recommended operating free-air temperature) Symbol fCK Description Operating clock frequency(1,2) Application clock frequency(3) AVDD, VDDQ = 2.5V ±0.2V Min. Max. 60 170 95 170 Units MHz tDC Input clock duty cycle 40 60 % www.DataSheet4UtS.cToAmB PLL stabilization time after powerup 100 µs Notes: 1. The PLL is able to handle spread spectrum induced skew. 2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not required to meet the other timing parameters. (Used for low-speed debug). 3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters. Electrical Characteristics for PC1600 ~ PC2700 (Over recommended operating free-air temperature) Parameter Test Conditions VIK All inputs VOH High output voltage VOL Low output voltage CLK, FBIN II PWRDWN II = –18mA IOH = –100µA IOH = –12mA IOL = 100µA IOL = 12mA VI = VDDQ or GND VI = VDDQ or GND IDDPD Static supply current IDDQ + IADD CLK & CLK = 0 MHz, PWRDWN = Low AVDD, VDDQ 2.3V 2.3 to 2.7V 2.3V 2.3 to 2.7V 2.3V 2.7V 2.7V Min. Typ. VDDQ– 0.1 1.7 Max. Units –1.2 V 0.1 0.6 ±10 µA 200 IDDQ Dynamic supply current of VDDQ CLK & CLK = 170 MHz All outputs are open 2.7V 300 mA IADD CI CI(∆) Dynamic supply current of AVDD CLK and CLK FBIN and FBIN CLK and CLK(5) FBIN and FBIN(5) CLK & CLK = 170 MHz VI = VDDQ or GND VI = VDDQ or GND 2.7V 2.5V 2.5V 2.0 –0.25 12 mA 3.5 pF 0.25 Note: 4. The maximum power-down clock frequency is below 20 MHz. 5. Guaranteed by design, but not production tested. 5 PS8683B 10/17/03 5 Page PI6CVF857 1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122 www.DataSheet4U.com Yx,FBOUT Yx,FBOUT tcycle n tcycle n+1 tjit(cc) = tcycle n - tcycle n+1 Figure 4. Cycle-to-Cycle Jitter CLK CLK FBIN FBIN t( ) n ∑n=N 1 t( ) n t= N t( ) n+1 (N > 1000 samples) Figure 5. Static Phase Offset Yx Yx Yx, FBOUT Yx, FBOUT t sk(o) Figure 6. Output Skew 11 PS8683B 10/17/03 11 Page

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