PDF TZA3052AHW Data sheet ( Hoja de datos )

Número de pieza	TZA3052AHW
Descripción	2.5 And 2.7 Gbits/s Fibre Optic Receiver
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET www.DataSheet4U.com TZA3052AHW 2.5 and 2.7 Gbits/s fibre optic receiver Product speciﬁcation Supersedes data of 2002 Aug 15 2003 May 14 1 page Philips Semiconductors 2.5 and 2.7 Gbits/s ﬁbre optic receiver Product speciﬁcation TZA3052AHW SYMBOL VCCD D13 D13Q D14 D14Q www.DataSheet4U.com D15 D15Q VCCD CLOOP CLOOPQ VCCD DLOOP DLOOPQ VCCD PIN DESCRIPTION 76 supply voltage (digital part) 77 parallel data output 13 78 parallel data output 13 inverted 79 parallel data output 14 80 parallel data output 14 inverted 81 parallel data output 15 82 parallel data output 15 inverted 83 supply voltage (digital part) 84 loop mode clock input 85 loop mode clock input inverted 86 supply voltage (digital part) 87 loop mode data input 88 loop mode data input inverted 89 supply voltage (digital part) SYMBOL ENLOUTQ ENLINQ TEMPAL VCCD COUT COUTQ VCCD DOUT DOUTQ VCCD VEE PIN DESCRIPTION 90 line loop back enable input (active LOW) 91 diagnostic loop back enable input (active LOW) 92 temperature alarm output 93 supply voltage (digital part) 94 recovered clock output 95 recovered clock output inverted 96 supply voltage (digital part) 97 recovered data output 98 recovered data output inverted 99 supply voltage (digital part) 100 ground 2003 May 14 5 5 Page Philips Semiconductors 2.5 and 2.7 Gbits/s ﬁbre optic receiver Product speciﬁcation TZA3052AHW handbook, halfpage ENBA www.DataSheet4U.com FP boundary detection enabled MGU340 handbook, halfpage ENBA FP boundary detection enabled MGU341 Fig.8 ENBA timing with section terminating device. Fig.9 Alternate ENBA timing. Parity generation Output pins PARITY and PARITYQ provide the EVEN parity of the byte/word that is currently available on the parallel bus. Loop mode I/Os The IC can be used in a ‘diagnostic loop back’ mode by setting pin ENLINQ to LOW. In this case, the demultiplexer will select inputs DLOOP and DLOOPQ, CLOOP and CLOOPQ instead of taking the input from the DCR. The ‘line loop back’ mode is activated by setting pin ENLOUTQ to LOW. Now, the recovered clock and serial data will be available at output pins DOUT and DOUTQ and COUT and COUTQ. RF I/Os The RF CML outputs have an amplitude of 80 mV (p-p) single-ended. The termination scheme is AC coupled (see Fig.11). CMOS control inputs Most CMOS control inputs have an internal pull-up resistor. If the input is required to be HIGH, it can be left open-circuit. Only the LOW state needs to be actively forced. This applies to pins WINSIZE, ENBA, ENLOUTQ, ENLINQ and DR. Power supply connections Four separate supply domains (VDD, VCCD, VCCO and VCCA) provide isolation between the various functional blocks. Each supply domain should be connected to a common VCC via separate filters. All supply pins, including the exposed die pad, must be connected. The die pad should be connected with the lowest inductance possible. Since the die pad is also used as the main ground return of the chip, the connection should have a low DC impedance as well. The voltage supply levels should be in accordance with the values specified in Chapter “Characteristics”. All external components should be surface mounted devices, preferably of size 0603 or smaller. The components must be mounted as closely to the IC as possible. Temperature alarm The TZA3052AHW features a temperature alarm. The temperature alarm switches the open-drain output of pin TEMPAL to LOW at a junction temperature above 130 °C. 2003 May 14 11 11 Page

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