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PDF CY62167E Data sheet ( Hoja de datos )
| Número de pieza | CY62167E | |
| Descripción | 16-Mbit (1M x 16 / 2M x 8) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CY62167E (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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CY62167E MoBL®
16-Mbit (1 M × 16 / 2 M × 8) Static RAM
16-Mbit (1 M × 16 / 2 M × 8) Static RAM
Features
■ Configurable as 1 M × 16 or as 2 M × 8 SRAM
■ Very high speed: 45 ns
■ Wide voltage range: 4.5 V to 5.5 V
■ Ultra low standby power
❐ Typical standby current: 1.5 µA
❐ Maximum standby current: 12 µA
■ Ultra low active power
❐ Typical active current: 2.2 mA at f = 1 MHz
■ Easy memory expansion with CE1, CE2, and OE features
■ Automatic power-down when deselected
■ CMOS for optimum speed and power
■ Offered in 48-pin TSOP I package
Functional Description
The CY62167E is a high performance CMOS static RAM
organized as 1 M words by 16-bits/2 M words by 8-bits. This
device features advanced circuit design to provide an ultra low
active current. This is ideal for providing More Battery Life
(MoBL®) in portable applications. The device also has an
automatic power down feature that reduces power consumption
when addresses are not toggling. Place the device into standby
mode when deselected (CE1 HIGH, or CE2 LOW, or both BHE
and BLE are HIGH). The input and output pins (I/O0 through
I/O15) are placed in a high impedance state when:
■ The device is deselected (CE1 HIGH or CE2 LOW)
■ Outputs are disabled (OE HIGH)
■ Both byte high enable and byte low enable are disabled (BHE,
BLE HIGH) or
■ A write operation is in progress (CE1 LOW, CE2 HIGH, and WE
LOW)
To write to the device, take chip enables (CE1 LOW and CE2
HIGH) and write enable (WE) input LOW. If byte low enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A19). If byte high enable (BHE) is LOW, then data from the I/O
pins (I/O8 through I/O15) is written into the location specified on
the address pins (A0 through A19).
To read from the device, take chip enables (CE1 LOW and CE2
HIGH) and output enable (OE) LOW while forcing the write
enable (WE) HIGH. If byte low enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O0 to I/O7. If byte high enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See Truth Table on page 12
for a complete description of read and write modes.
The CY62167E device is suitable for interfacing with processors
that have TTL I/P levels. It is not suitable for processors that
require CMOS I/P levels. Please see Electrical Characteristics
on page 4 for more details and suggested alternatives.
For a complete list of related documentation, click here.
Logic Block Diagram
A10
A9
A
A
A
8
7
6
A5
A4
A3
A2
A
A
1
0
DATA IN DRIVERS
1 M × 16 / 2 M × 8
RAM ARRAY
I/O0–I/O7
I/O8–I/O15
POWER DOWN
CIRCUIT
CE2
CE1
BHE
BLE
COLUMN DECODER
BYTE
BHE
WE
OE
BLE
CE2
CE1
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-15607 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 20, 2015
1 page  
CY62167E MoBL®
Capacitance
Parameter [11]
Description
CIN
COUT
Input capacitance
Output capacitance
Thermal Resistance
Parameter [11]
Description
ΘJA Thermal resistance
(junction to ambient)
ΘJC Thermal resistance
(junction to case)
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max Unit
10 pF
10 pF
Test Conditions
48-pin TSOP I Unit
Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
54.25
°C/W
12.63
°C/W
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms
VCC
OUTPUT
R1
30 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
VCC
GND
10%
90%
90%
10%
R2 RISE TIME= 1 V/ns
FALL TIME= 1 V/ns
EQUIVALENT TO: THÉVENIN EQUIVALENT
OUTPUT
RTH
VTH
Parameters
R1
R2
RTH
VTH
Values
1800
990
639
1.77
Unit
Ω
Ω
Ω
V
Note
11. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-15607 Rev. *G
Page 5 of 18
5 Page 
CY62167E MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle No. 4 (BHE/BLE controlled, OE LOW) [36]
ADDRESS
tWC
CE1
CE2
BHE/BLE
WE
tSA
DATA I/O
NOTE 37
tSCE
tAW
tBW
tPWE
tSD
VALID DATA
tHA
tHD
Notes
36. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
37. During this period the I/Os are in output state and input signals must not be applied.
Document Number: 001-15607 Rev. *G
Page 11 of 18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CY62167E.PDF ] | |
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