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PDF PLL103-53 Data sheet ( Hoja de datos )
| Número de pieza | PLL103-53 | |
| Descripción | DDR SDRAM Buffer | |
| Fabricantes | PhaseLink Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PLL103-53 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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Preliminary PLL103-53
DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS
FEATURES
• Generates 30-output buffers from one input.
• Supports up to 4 DDR DIMMS or 3 SDR DIMMS
and 2 DDR DIMMS.
• Supports 266MHz DDR SDRAM.
• One additional output for feedback.
• Less than 5ns delay.
• Skew between any outputs is less than 100 ps.
www.DataShee•t4U.2co.m5V or 3.3V Supply range.
• Enhanced DDR and SDRAM Output Drive
selected by I2C.
• Available in 56 pin SSOP.
PIN CONFIGURATION
FBOUT
VDD3.3_2.5
GND
DDR0T_SDRAM10
DDR0C_SDRAM11
DDR1T_SDRAM0
DDR1C_SDRAM1
VDD3.3_2.5
GND
DDR2T_SDRAM2
DDR2C_SDRAM3
VDD3.3_2.5
BUF_IN
GND
DDR3T_SDRAM4
DDR3C_SDRAM5
VDD3.3_2.5
GND
DDR4T_SDRAM6
DDR4C_SDRAM7
DDR5T_SDRAM8
DDR5C_SDRAM9
VDD3.3_2.5
SDATA
GND
VDD2.5
DDR12T
DDR12C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Note: #: Active Low
56 SEL_DDR
55 VDD2.5
54 GND
53 DDR11T
52 DDR11C
51 DDR10T
50 DDR10C
49 VDD2.5
48 GND
47 DDR9T
46 DDR9C
45 VDD2.5
44 PD#
43 GND
42 DDR8T
41 DDR8C
40 VDD2.5
39 GND
38 DDR7T
37 DDR7C
36 DDR6T
35 DDR6C
34 GND
33 SCLK
32 VDD2.5
31 GND
30 DDR13C
29 DDR13T
BLOCK DIAGRAM
SDATA
SCLK
I2C
Control
BUF_IN
PD#
DESCRIPTIONS
DDR0T_SDRAM10
DDR0C_SDRAM11
DDR1T_SDRAM0
DDR1C_SDRAM1
DDR2T_SDRAM2
DDR2C_SDRAM3
DDR3T_SDRAM4
DDR3C_SDRAM5
DDR4T_SDRAM6
DDR4C_SDRAM7
DDR5T_SDRAM8
DDR5C_SDRAM9
DDR(6:13)T
DDR(6:13)C
FBOUT
The PLL103-53 is designed as a 3.3V/2.5V buffer to
distribute high-speed clocks in PC applications. The
device has 30 outputs. These outputs can be
configured to support 4 unbuffered DDR (Double
Data Rate) DIMMS or to support 3 unbuffered
standard SDR (Single Data Rate) DIMMS and 2 DDR
DIMMS. The PLL103-53 can be used in conjunction
with the PLL202-14/-54 or similar clock synthesizer
for the VIA Pro 266 chipset.
The PLL103-53 also has an I2C interface, which can
enable or disable each output clock. When power up,
all output clocks are enabled (has internal pull up).
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 12/01/00 Page 1
1 page  
Preliminary PLL103-53
DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
Input Voltage, dc
www.DataSheOetu4tUpu.ctoVmoltage, dc
Storage Temperature
Ambient Operating Temperature
ESD Voltage
VDD VSS-0.5 7.0
V
VI
VSS-0.5
VDD+0.5
V
VO
VSS-0.5
VDD+0.5
V
TS -65 150 °C
TA 0 70 °C
2 KV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
2. Operating Conditions
Supply Voltage
Supply Voltage
Input Capacitance
Output Capacitance
PARAMETERS
SYMBOL
VDD3.3
VDD2.5
CIN
COUT
MIN.
3.135
2.375
MAX.
3.465
2.625
5
6
UNITS
V
V
pF
pF
3. Electrical Specifications
PARAMETERS SYMBOL
CONDITIONS
MIN.
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High
Voltage
Output Low
Voltage
Output High
Current
Output Low
Current
VIH All Inputs except I2C
VIL All inputs except I2C
IIH VIN = VDD
IIL VIN = 0
VOH IOL = -12mA,
VDD = 2.375V
VOL IOL = 12mA,
VDD = 2.375V
IOH VDD = 2.375V, VOUT=1V
IOL VDD = 2.375V, VOUT=1.2V
2.0
VSS-0.3
1.7
-18
26
Note: TBM: To be measured
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
TYP.
-32
35
MAX.
VDD+0.3
0.8
TBM
TBM
UNITS
V
V
uA
uA
V
0.6 V
mA
mA
Rev 12/01/00 Page 5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PLL103-53.PDF ] | |
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