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PDF PLL103-11 Data sheet ( Hoja de datos )
| Número de pieza | PLL103-11 | |
| Descripción | Low Skew Buffers | |
| Fabricantes | PhaseLink Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PLL103-11 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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FEATURES
• Generates 13 copies of High-speed clock inputs.
• Supports up to three SDRAM DIMMS synchronous
clocks.
• Supports 2-wire I2C serial bus interface with
readback.
• 50% duty cycle with low jitter.
• Less than 5ns delay.
www.DataShe•et4U.Scokmew between any outputs is less than 250 ps.
• Tri-state pin for testing.
• Frequency up to 150 MHz.
• 3.0V-3.7V Supply range.
• Available in 28-pin 300mil SOIC package.
BLOCK DIAGRAM
PLL103-11
Low Skew Buffers
PIN CONFIGURATION
VDD
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
GND
BUF_IN
SDRAM4
SDRAM5
SDRAM12
VDD1
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VDD
27 SDRAM11
26 SDRAM10
25 GND
24 VDD
23 SDRAM9
22 SDRAM8
21 GND
20 VDD
19 SDRAM7
18 SDRAM6
17 GND
16 GND1
15 SCLK
SDATA
SCLK
I2C
Control
BUF_IN
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
POWER GROUP
• VDD: SDRAM (0:12)
• VDD1: I2C Circuitry
GROUND GROUP
• GND: SDRAM (0:12)
• GND1: I2C Circuitry
KEY SPECIFICATIONS
• BUF_IN to SDRAM outputs Delay: 1 ~ 5 ns.
• Output Slew: ≥1.5 V/ns.
• Output Skew: ±250 ps.
• Output Duty Cycle: 50% ± 5%.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/07/00 Page 1
1 page  
PLL103-11
Low Skew Buffers
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
Input Voltage, dc
www.DataSheOetu4tUp.uctoVmoltage, dc
Storage Temperature
Ambient Operating Temperature
VDD VSS-0.5 7.0
V
VI
VSS-0.5
VDD+0.5
V
VO
VSS-0.5
VDD+0.5
V
TS -65 150 °C
TA 0 70 °C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
2. AC/DC Electrical Specifications
PARAMETERS
Input High Current
Input Low Current
Input High Voltage
Input Low Voltage
Input Frequency
Input Capacitance
Operating Supply
Current
SYMBOL
CONDITIONS
IIH VIN = VDD
IIL VIN=0V; with no pull-up resistors
IIL VIN=0V; with 100k pull-up resistors
VIH
VIL
FIN VDD=3.3V; All outputs loaded
CIN Logic Inputs
IDD1 CL= 0pf @ 66MHz
IDD2 CL= 0pf @ 100MHz
IDD3 CL= 30pf; RS= 33Ω @ 66MHz
IDD4 CL= 30pf; RS= 33Ω @ 100MHz
IDD5 Stopped, input at 0 or VDD
MIN.
2
VSS−0.3
10
TYP.
80
120
180
240
MAX.
5
VDD+0.3
0.8
150
5
120
180
260
360
500
UNITS
uA
uA
uA
V
V
MHz
pF
mA
mA
mA
mA
uA
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/07/00 Page 5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PLL103-11.PDF ] | |
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