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PDF HT48CU80 Data sheet ( Hoja de datos )
| Número de pieza | HT48CU80 | |
| Descripción | (HT48RU80 / HT48CU80) I/O Type 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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HT48RU80/HT48CU80
I/O Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0004E HT48 & HT46 MCU UART Software Implementation Method
- HA0013E HT48 & HT46 LCM Interface Design
- HA0021E Using the I/O Ports on the HT48 MCU Series
www.DataSheet4U.com
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· Low voltage reset function
· 56 bidirectional I/O lines (max.)
· Two interrupt input
· 16-bit´2 programmable timer/event counter and
overflow interrupts with PFD outputs
· 8-bit´1 programmable timer/event counter
· On-chip RC oscillator, external crystal and RC oscil-
lator
· 32768Hz crystal oscillator for timing purposes only
· Watchdog Timer
· 16K´16 program memory ROM
· 576´8 data memory RAM
· Universal Asynchronous Receiver/Transmitter
(UART)
· HALT function and wake-up feature reduce power
consumption
· 16-level subroutine nesting
· Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
· Bit manipulation instruction
· 16-bit table read instruction
· 63 powerful instructions
· All instructions in one or two machine cycles
· 48-pin SSOP, 64-pin QFP package
General Description
The HT48RU80/HT48CU80 are 8-bit high performance,
RISC architecture microcontroller devices specifically
designed for multiple I/O control product applications.
The mask version HT48CU80 is fully pin and function-
ally compatible with the OTP version HT48RU80 de-
vice.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, HALT and
wake-up functions, watchdog timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem con-
trollers, etc.
The HT48CU80 is under development and will be avail-
able soon.
Rev. 1.00
1 April 12, 2006
1 page  
HT48RU80/HT48CU80
D.C. Characteristics
Ta=25°C
Symbol
Parameter
VDD Operating Voltage
IDD1 Operating Current (Crystal OSC)
Test Conditions
VDD Conditions
¾ fSYS=4MHz
¾ fSYS=8MHz
3V
No load, fSYS=4MHz
5V
Min. Typ. Max. Unit
2.2 ¾ 5.5 V
3.3 ¾ 5.5 V
¾ 0.6 1.5 mA
¾2
4 mA
IDD2
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IDD3
Operating Current (RC OSC)
Operating Current
(Crystal OSC, RC OSC)
3V ¾ 0.8 1.5 mA
No load, fSYS=4MHz
5V ¾ 2.5 4 mA
5V No load, fSYS=8MHz
¾
4
8 mA
3V ¾ ¾ 5 mA
ISTB1 Standby Current (WDTOSC On, RTC Off)
No load, system HALT
5V ¾ ¾ 10 mA
3V ¾ ¾ 1 mA
ISTB2 Standby Current (WDTOSC Off, RTC Off)
No load, system HALT
5V ¾ ¾ 2 mA
ISTB3
VIL1
VIH1
VIL2
VIH2
VLVR
IOL
IOH
RPH
3V ¾ ¾ 5 mA
Standby Current (WDTOSC Off, RTC On)
No load, system HALT
5V ¾ ¾ 10 mA
Input Low Voltage for I/O Ports
¾¾
0 ¾ 0.3VDD V
Input High Voltage for I/O Ports ¾ ¾ 0.7VDD ¾ VDD V
Input Low Voltage (RES)
¾¾
0 ¾ 0.4VDD V
Input High Voltage (RES)
¾ ¾ 0.9VDD ¾ VDD V
Low Voltage Reset
¾ LVR enabled
2.7 3.0 3.3
V
I/O Port Sink Current
3V VOL=0.1VDD
5V VOL=0.1VDD
4 8 ¾ mA
10 20 ¾ mA
I/O Port Source Current
3V VOH=0.9VDD
5V VOH=0.9VDD
-2 -4 ¾ mA
-5 -10 ¾ mA
Pull-high Resistance
3V
¾
5V
20 60 100 kW
10 30 50 kW
Rev. 1.00
5 April 12, 2006
5 Page 
HT48RU80/HT48CU80
Bit No.
0
www.DataSheet4U.com
1
2
3
4
5
6~7
Label
C
AC
Z
OV
PDF
TO
¾
Function
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation, otherwise C is cleared. C is also affected by a ro-
tate through carry instruction.
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction, otherwise AC is cleared.
Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa, otherwise OV is cleared.
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
Unused bit, read as ²0².
Status (0AH) Register
give different results from those intended. The TO
flag can be affected only by a system power-up, a
WDT time-out or executing the ²CLR WDT² or
²HALT² instruction. The PDF flag can be affected
only by executing the ²HALT² or ²CLR WDT² instruc-
tion or during a system power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or exe-
cuting a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can cor-
rupt the status register, precautions must be taken to
save it properly.
Interrupt
The device provides two external interrupts, three inter-
nal timer/event counter interrupts, and a UART TX/ RX
interrupt. The Interrupt Control Register 0 (INTC0; 0BH)
and Interrupt Control Register 1 (INTC1;1EH) both con-
tain the interrupt control bits that are used to set the en-
able/disable status and interrupt request flags.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC0 or INTC1
may be set to allow interrupt nesting. If the stack is full,
the interrupt request will not be acknowledged, even if
the related interrupt is enabled, until the SP is decre-
mented. If immediate service is desired, the stack must
be prevented from becoming full.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the pro-
gram memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the con-
tents should be saved in advance.
External interrupts are triggered by a high to low transi-
tion of the INT0 or INT1 and the related interrupt request
flag (EIF0; bit 4 of the INTC0; EIF1; bit 4 of the INTC1)
will be set. When the interrupt is enabled, the stack is
not full and the external interrupt is active, a subroutine
call to location 04H or 10H will occur. The interrupt re-
quest flag (EIF0 or EIF1) and EMI bits will be cleared to
disable other interrupts.
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (T0F; bit 5 of the INTC0), caused by a timer 0
overflow. When the interrupt is enabled, the stack is not
full and the T0F bit is set, a subroutine call to location
08H will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable further in-
terrupts.
The internal Timer/Event Counter 1 interrupt is initial-
ized by setting the Timer/Event Counter 1 interrupt re-
quest flag (T1F; bit 6 of the INTC0), caused by a T 1
overflow. When the interrupt is enabled, the stack is not
full and the T1F is set, a subroutine call to location 0CH
will occur. The related interrupt request flag (T1F) will be
reset and the EMI bit cleared to disable further inter-
rupts.
The UART interrupt is initialized by setting the interrupt
request flag (URF; bit 5 of the INTC1), that is caused by
a regular UART receive signal, caused by a UART
transmit signal. After the interrupt is enabled, the stack
is not full, and the URF bit is set, a subroutine call to lo-
cation 14H occurs. The related interrupt request flag
(URF) is reset and the EMI bit is cleared to disable fur-
ther other interrupts.
Rev. 1.00
11 April 12, 2006
11 Page | ||
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