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PDF ST10F269-Q3 Data sheet ( Hoja de datos )
| Número de pieza | ST10F269-Q3 | |
| Descripción | 16-BIT MCU | |
| Fabricantes | STMicroelectronics | |
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ST10F269
16-BIT MCU WITH MAC UNIT, 256K BYTE FLASH MEMORY AND 12K BYTE RAM
PRELIMINARY DATA
s HIGH PERFORMANCE 40MHz CPU WITH DSP
FUNCTION
– 16-BIT CPU WITH 4-STAGE PIPELINE
– 50ns INSTRUCTION CYCLE TIME AT 40MHz MAX
CPU CLOCK
– MULTIPLY/ACCUMULATE UNIT (MAC) 16 x 16-BIT
MULTIPLICATION, 40-BIT ACCUMULATOR
– REPEAT UNIT
– ENHANCED BOOLEAN BIT MANIPULATION FA-
CILITIES
– ADDITIONAL INSTRUCTIONS TO SUPPORT HLL
AND OPERATING SYSTEMS
– SINGLE-CYCLE CONTEXT SWITCHING SUP-
PORT
s MEMORY ORGANIZATION
– 256K BYTE ON-CHIP FLASH MEMORY SINGLE
VOLTAGE WITH ERASE/PROGRAM CONTROLLER.
– 100K ERASING/PROGRAMMING CYCLES.
– UP TO 16M BYTE LINEAR ADDRESS SPACE FOR
CODE AND DATA (5M BYTES WITH CAN)
– 2K BYTE ON-CHIP INTERNAL RAM (IRAM)
– 10K BYTE ON-CHIP EXTENSION RAM (XRAM)
s FAST AND FLEXIBLE BUS
– PROGRAMMABLE EXTERNAL BUS CHARACTE-
RISTICS FOR DIFFERENT ADDRESS RANGES
– 8-BIT OR 16-BIT EXTERNAL DATA BUS
– MULTIPLEXED OR DEMULTIPLEXED EXTERNAL
ADDRESS/DATA BUSES
– FIVE PROGRAMMABLE CHIP-SELECT SIGNALS
– HOLD-ACKNOWLEDGE BUS ARBITRATION SUP-
PORT
s INTERRUPT
– 8-CHANNEL PERIPHERAL EVENT CONTROLLER
FOR SINGLE CYCLE INTERRUPT DRIVEN DATA
TRANSFER
– 16-PRIORITY-LEVEL INTERRUPT SYSTEM WITH
56 SOURCES, SAMPLING RATE DOWN TO 25ns
s TIMERS
– TWO MULTI-FUNCTIONAL GENERAL PURPOSE
TIMER UNITS WITH 5 TIMERS
s TWO 16-CHANNEL CAPTURE / COMPARE UNITS
s A/D CONVERTER
– 16-CHANNEL 10-BIT
– 4.85µs CONVERSION TIME AT 40MHz CPU CLOCK
s 4-CHANNEL PWM UNIT
s SERIAL CHANNELS
– SYNCHRONOUS / ASYNCHRONOUS SERIAL
CHANNEL
– HIGH-SPEED SYNCHRONOUS CHANNEL
PQFP144 (28 x 28 mm)
(Plastic Quad Flat Pack)
ORDER CODE: ST10F269-Q3
s TWO CAN 2.0B INTERFACES OPERATING ON ONE
OR TWO CAN BUSSES (30 OR 2x15 MESSAGE
OBJECTS)
s FAIL-SAFE PROTECTION
– PROGRAMMABLE WATCHDOG TIMER
– OSCILLATOR WATCHDOG
s ON-CHIP BOOTSTRAP LOADER
s CLOCK GENERATION
– ON-CHIP PLL
– DIRECT OR PRESCALED CLOCK INPUT
s REAL TIME CLOCK
s UP TO 111 GENERAL PURPOSE I/O LINES
– INDIVIDUALLY PROGRAMMABLE AS INPUT,
OUTPUT OR SPECIAL FUNCTION
– PROGRAMMABLE THRESHOLD (HYSTERESIS)
s IDLE AND POWER DOWN MODES
s SINGLE VOLTAGE SUPPLY: 5V ±10% (EMBEDDED
REGULATOR FOR 3.3 V CORE SUPPLY).
s TEMPERATURE RANGE: -40 +125°C
s 144-PIN PQFP PACKAGE
256K Byte
Flash Memory
32
CPU-Core and MAC Unit
10K Byte
XRAM
CAN1_RXD
CAN1_TXD
CAN2_RXD
CAN2_TXD
CAN1
CAN2
16
PEC
Interrupt Controller
16
16
2K Byte
Internal
RAM
Watchdog
Oscillator
and PLL
XTAL1 XTAL2
16
3.3V Voltage
Regulator
16
16
8
Port 6
8
Port 5
16
BRG
BRG
Port 3
15
Port 7
8
16
Port 8
8
September 2013
DocID7588 Rev 3
1/160
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1 page  
ST10F269
TABLE OF CONTENTS
PAGE
20 - SPECIAL FUNCTION REGISTER OVERVIEW ......................................................... 117
20.1 -
IDENTIFICATION REGISTERS ................................................................................. 123
20.2 -
SYSTEM CONFIGURATION REGISTERS ................................................................ 124
21 - ELECTRICAL CHARACTERISTICS .........................................................................
21.1 -
ABSOLUTE MAXIMUM RATINGS .............................................................................
21.2 -
PARAMETER INTERPRETATION .............................................................................
21.3 -
21.3.1 -
21.3.2 -
DC CHARACTERISTICS ...........................................................................................
A/D Converter Characteristics ....................................................................................
Conversion Timing Control .......................................................................................
21.4 -
21.4.1 -
21.4.2 -
21.4.3 -
21.4.4 -
21.4.5 -
21.4.6 -
21.4.7 -
21.4.8 -
21.4.9 -
21.4.10 -
21.4.11 -
21.4.12 -
21.4.13 -
21.4.14 -
21.4.14.1
21.4.14.2
AC CHARACTERISTICS ............................................................................................
Test Waveforms .......................................................................................................
Definition of Internal Timing ........................................................................................
Clock Generation Modes ............................................................................................
Prescaler Operation ....................................................................................................
Direct Drive .................................................................................................................
Oscillator Watchdog (OWD) .......................................................................................
Phase Locked Loop ....................................................................................................
External Clock Drive XTAL1 .......................................................................................
Memory Cycle Variables .............................................................................................
Multiplexed Bus ..........................................................................................................
Demultiplexed Bus ......................................................................................................
CLKOUT and READY .................................................................................................
External Bus Arbitration ..............................................................................................
High-Speed Synchronous Serial Interface (SSC) Timing ...........................................
Master Mode................................................................................................................
Slave mode..................................................................................................................
131
131
131
131
134
135
136
136
136
137
138
138
138
138
139
140
141
147
153
155
157
157
158
22 - PACKAGE MECHANICAL DATA ........................................................................... 159
23 - ORDERING INFORMATION ...................................................................................... 159
5/160
5 Page 
ST10F269
Symbol
Pin Type
Function
P0L.0 - P0L.7, 100-107, I/O Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or
P0H.0
108,
output via direction bit. Programming an I/O pin as input forces the corresponding
P0H.1 - P0H.7 111-117
output driver to high impedance state.
In case of an external bus configuration, PORT0 serves as the address (A) and as
the address / data (AD) bus in multiplexed bus modes and as the data (D) bus in
demultiplexed bus modes.
Demultiplexed bus modes
Data Path Width:
P0L.0 – P0L.7:
P0H.0 – P0H.7
8-bit
D0 – D7
I/O
Multiplexed bus modes
16-bit
D0 - D7
D8 - D15
Data Path Width:
P0L.0 – P0L.7:
P0H.0 – P0H.7
8-bit
16-bit
AD0 – AD7 AD0 - AD7
A8 – A15 AD8 - AD15
P1L.0 - P1L.7 118-125
P1H.0 - P1H.7 128-135
I/O Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. PORT1 is used as the 16-bit address bus (A)
in demultiplexed bus modes and also after switching from a demultiplexed bus mode
to a multiplexed bus mode.
The following PORT1 pins have alternate functions:
132 I P1H.4 CC24IO
CAPCOM2: CC24 Capture Input
133 I P1H.5 CC25IO
CAPCOM2: CC25 Capture Input
134 I P1H.6 CC26IO
CAPCOM2: CC26 Capture Input
135 I P1H.7 CC27IO
CAPCOM2: CC27 Capture Input
XTAL1
138 I XTAL1 Oscillator amplifier and/or external clock input.
XTAL2
137 O XTAL2 Oscillator amplifier circuit output.
To clock the device from an external source, drive XTAL1 while leaving XTAL2
unconnected. Minimum and maximum high / low and rise / fall times specified in the
AC Characteristics must be observed.
RSTIN
140 I Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified
duration while the oscillator is running resets the ST10F269. An internal pull-up
resistor permits power-on reset using only a capacitor connected to VSS. In bidirec-
tional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the
RSTIN line is pulled low for the duration of the internal reset sequence.
RSTOUT
141 O Internal Reset Indication Output. This pin is driven to a low level during hardware,
software or watchdog timer reset. RSTOUT remains low until the EINIT (end of ini-
tialization) instruction is executed.
NMI 142 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to
vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the
PWRDN (power down) instruction is executed, the NMI pin must be low in order to
force the ST10F269 to go into power down mode. If NMI is high and PWDCFG =’0’,
when PWRDN is executed, the part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
VAREF
37 - A/D converter reference voltage.
VAGND
38 - A/D converter reference ground.
RPD
84 - Timing pin for the return from interruptible powerdown mode and synchronous /
asynchronous reset selection.
11/160
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| PDF Descargar | [ Datasheet ST10F269-Q3.PDF ] | |
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