PDF CY7C1470BV25 Data sheet ( Hoja de datos )

Número de pieza	CY7C1470BV25
Descripción	(CY7C147xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM
Fabricantes	Cypress Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de CY7C1470BV25 (archivo pdf) en la parte inferior de esta página. Total 29 Páginas
No Preview Available ! CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Features ■ Pin-compatible and functionally equivalent to ZBT™ ■ Supports 250 MHz bus operations with zero wait states ❐ Available speed grades are 250, 200, and 167 MHz ■ Internally self-timed output buffer control to eliminate the need to use asynchronous OE www.DataSheet4U.com ■ Fully registered (inputs and outputs) for pipelined operation ■ Byte Write capability ■ Single 2.5V power supply ■ 2.5V IO supply (VDDQ) ■ Fast clock-to-output times ❐ 3.0 ns (for 250-MHz device) ■ Clock Enable (CEN) pin to suspend operation ■ Synchronous self-timed writes ■ CY7C1470BV25, CY7C1472BV25 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1474BV25 available in Pb-free and non-Pb-free 209-ball FBGA package ■ IEEE 1149.1 JTAG Boundary Scan compatible ■ Burst capability—linear or interleaved burst order ■ “ZZ” Sleep Mode option and Stop Clock option Functional Description The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read or write operations with no wait states. The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are equipped with the advanced (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent read or write transitions. The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are pin-compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects (BWa–BWd for CY7C1470BV25, BWa–BWb for CY7C1472BV25, and BWa–BWh for CY7C1474BV25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 250 MHz 3.0 450 120 200 MHz 3.0 450 120 167 MHz 3.4 400 120 Unit ns mA mA Cypress Semiconductor Corporation • 198 Champion Court Document #: 001-15032 Rev. D • San Jose, CA 95134-1709 • 408-943-2600 Revised February 29, 2008 [+] Feedback 1 page CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Pin Configurations (continued) 1 A NC/576M B C www.DataSheet4U.com D E F G H J K L M N P NC/1G DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC/144M R MODE 2 A A NC DQc DQc DQc DQc NC DQd DQd DQd DQd NC A A 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1470BV25 (2M x 36) 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 7 CEN WE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADV/LD OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A 11 NC NC DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa NC/288M A 1 A NC/576M 2 A B NC/1G A C NC NC D NC DQb E NC DQb F NC DQb G NC DQb H NC NC J DQb NC K DQb NC L DQb NC M DQb NC N DQPb NC P NC/144M A R MODE A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A CY7C1472BV25 (4M x 18) 4 BWb NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 7 CEN WE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADV/LD OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A 11 A NC DQPa DQa DQa DQa DQa ZZ NC NC NC NC NC NC/288M A Document #: 001-15032 Rev. D Page 5 of 29 [+] Feedback 5 Page CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Table 5. Partial Write Cycle Description The partial write cycle description for CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 follows.[1, 2, 3, 8] Function (CY7C1470BV25) Read Write – No bytes written Write Byte a – (DQa and DQPa) Write Byte b – (DQb and DQPb) Write Bytes b, a www.DataSheWert4itUe.Bcoymte c – (DQc and DQPc) Write Bytes c, a Write Bytes c, b Write Bytes c, b, a Write Byte d – (DQd and DQPd) Write Bytes d, a Write Bytes d, b Write Bytes d, b, a Write Bytes d, c Write Bytes d, c, a Write Bytes d, c, b Write All Bytes WE BWd BWc BWb HXXX L HHH L HHH L HH L L HH L LHLH LHLH L H LL L LHL L L LHH L LHH L LHL L LHL L L LH L L LH LLLL LLLL BWa X H L H L H L H L H L H L H L H L Function (CY7C1472BV25) Read Write – No Bytes Written Write Byte a – (DQa and DQPa) Write Byte b – (DQb and DQPb) Write Both Bytes WE H L L L L BWb x H H L L BWa x H L H L Function (CY7C1474BV25) Read Write – No Bytes Written Write Byte X − (DQx and DQPx) Write All Bytes WE BWx Hx LH LL L All BW = L Note 8. Table lists only a partial listing of the Byte Write combinations. Any combination of BW[a:d] is valid. Appropriate write is based on which Byte Write is active. Document #: 001-15032 Rev. *D Page 11 of 29 [+] Feedback 11 Page

Páginas	Total 29 Páginas
PDF Descargar	[ Datasheet CY7C1470BV25.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
CY7C1470BV25	(CY7C147xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM	Cypress Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar