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PDF PPC405GPR Data sheet ( Hoja de datos )
| Número de pieza | PPC405GPR | |
| Descripción | Power PC 405GPr Embedded Processor | |
| Fabricantes | AMCC | |
| Logotipo |  |
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Part Number 405GPr
Revision 2.04 – September 7, 2007
405GPr
Power PC 405GPr Embedded Processor
Data Sheet
Features
• PowerPC® 405 32-bit RISC processor core
operating up to 400MHz with 16KB I- and
D-caches
• Synchronous DRAM (SDRAM) interface operating
www.DataSheet4U.cuopmto 133MHz
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8
check bits for ECC applications
• 4KB on-chip memory (OCM)
• External peripheral bus
- Flash ROM/Boot ROM interface
- Direct support for 8-, 16-, or 32-bit SRAM and
external peripherals
- Up to eight devices
- External Mastering supported
• DMA support for external peripherals, internal
UART and memory
- Scatter-gather chaining supported
- Four channels
• PCI Revision 2.2 compliant interface (32-bit, up to
66 MHz)
- Synchronous or asynchronous PCI Bus
interface
- Internal or external PCI Bus Arbiter
• Ethernet 10/100Mbps (full-duplex) support with
media independent interface (MII)
• Programmable interrupt controller supports 13
external and 19 internal edge triggered or level-
sensitive interrupts
• Programmable timers
• Two serial ports (16550 compatible UART)
• One IIC interface
• General purpose I/O (GPIO) available
• Supports JTAG for board level testing
• Internal processor local Bus (PLB) runs at SDRAM
interface frequency
• Supports PowerPC processor boot from PCI
memory
• Unique software-accessible 64-bit chip ID number
(ECID).
Description
Designed specifically to address embedded
applications, the PowerPC 405GPr (PPC405GPr)
provides a high-performance, low-power solution that
interfaces to a wide range of peripherals by
incorporating on-chip power management features
and lower power dissipation requirements.
This chip contains a high-performance RISC
processor core, SDRAM controller, PCI bus interface,
Ethernet interface, control for external ROM and
peripherals, DMA with scatter-gather support, serial
ports, IIC interface, and general purpose I/O.
Technology: CMOS SA-27E, 0.18 μm
(0.11 μm Leff)
Package: 456-ball (35mm or 27mm) enhanced plastic
ball grid array (E-PBGA) in both leaded and lead-free
versions
Power (typical): 0.72W at 266MHz
AMCC
1
1 page  
Revision 2.04 – September 7, 2007
Data Sheet
405GPr – Power PC 405GPr Embedded Processor
Order Part Number Key
PPC405GPr-3BB266x
Part Number
Grade 3 Reliability
www.DataSheet4U.com
Package and Operational Case Temperature
B: 35mm, 456 E-PBGA, -40°C to +85°C
D: 27mm, 456 E-PBGA, -40°C to +85°C
J: 35mm, 456 E-PBGA lead-free, -40°C to +85°C
K: 27mm, 456 E-PBGA lead-free, -40°C to +85°C
Shipping Package
Blank = Tray
Z = Tape and reel
Processor Speed
266 MHz
333 MHz
400 MHz
Revision Level
AMCC
5
5 Page 
Revision 2.04 – September 7, 2007
Data Sheet
405GPr – Power PC 405GPr Embedded Processor
- Programmable CSon, CSoff relative to address
- Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS
• Programmable address mapping
• Peripheral Device pacing with external “Ready”
• External master interface
- Write posting from external master
- Read prefetching on PLB for external master reads
www.DataSheet4U.com- Bursting capable from external master
- Allows external master access to all non-EBC PLB slaves
- External master can control EBC slaves for own access and control
DMA Controller
• Supports the following transfers:
- Memory-to-memory transfers
- Buffered peripheral to memory transfers
- Buffered memory to peripheral transfers
• Four channels
• Scatter/gather capability for programming multiple DMA operations
• 8-, 16-, 32-bit peripheral support (OPB and external)
• 32-bit addressing
• Address increment or decrement
• Internal 32-byte data buffering capability
• Supports internal and external peripherals
• Support for memory mapped peripherals
• Support for peripherals running on slower frequency buses
AMCC
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PPC405GPR.PDF ] | |
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