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PDF CY7C1049BNV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1049BNV33 | |
| Descripción | 512K x 8 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1049BNV33
512K x 8 Static RAM
Features
• High speed
— tAA = 12 ns
• Low active power
— 504 mW (max.)
• Low CMOS standby power (Commercial L version)
www.DataSheet4U.com
— 1.8 mW (max.)
• 2.0V Data Retention (660 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CE
WE
OE
INPUTBUFFER
512K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Functional Description[1]
The CY7C1049BNV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049BNV33 is available in a standard 400-mil-wide
36-pin SOJ and 44-pin TSOPII packages with center power
and ground (revolutionary) pinout.
Pin Configuration
SOJ
Top View
TSOP
Top View
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36 NC
NC 1
35 A18
34 A17
33 A16
32 A15
31 OE
NC 2
A0 3
A1 4
A2 5
A3 6
A4 7
30 I/O7 CE 8
29 I/O6 I/O0 9
28
27
26
GND
VCC
I/O5
I/O1
VCC
VSS
I/O2
10
11
12
13
25 I/O4 I/O3 14
24 A14
23 A13
22 A12
21 A11
20 A10
WE 15
A5 16
A6 17
A7 18
A8 19
A9 20
19 NC
NC 21
NC 22
44 NC
43 NC
42 NC
41 A18
40 A17
39 A16
38 A15
37 OE
36 I/O7
35 I/O6
34 VSS
33 VCC
32 I/O5
31 I/O4
30 A14
29 A13
28 A12
27 A11
26 A10
25 NC
24 NC
23 NC
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06432 Rev. **
Revised February 1, 2006
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Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled, OE HIGH During Write)[15, 16]
ADDRESS
CE
WE
www.DataSheet4U.com
tWC
tSCE
tAW
tSA tPWE
OE
DATA I/O
NOTE 17
tHZOE
Write Cycle No. 2 (WE Controlled, OE LOW)[16]
tSD
DATAIN VALID
ADDRESS
CE
tWC
tSCE
CY7C1049BNV33
tHA
tHD
tSA
WE
DATA I/O
NOTE 17
tHZWE
tAW
tPWE
tSD
DATA VALID
Truth Table
CE OE WE
I/O0 – I/O7
H X X High Z
Power-Down
Mode
L L H Data Out
Read
L X L Data In
Write
L H H High Z
Selected, Outputs Disabled
Notes:
15. Data I/O is high-impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
17. During this period the I/Os are in the output state and input signals should not be applied.
tHA
tHD
tLZWE
Power
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Document #: 001-06432 Rev. **
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